Greg A Rausch

US Patent:

7612620, Nov 3, 2009

Filed:

Jun 29, 2007

Appl. No.:

11/824075

Inventors:

Greg Rausch - Plymouth MN, US
Robert Rabe - Chanhassen MN, US
Curtis Schnarr - Shoreview MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03B 27/00
H03K 3/017
H03K 5/04

US Classification:

331 45, 327144, 327175

Abstract:

A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals.

US Patent:

20070300111, Dec 27, 2007

Filed:

May 25, 2006

Appl. No.:

11/442515

Inventors:

Greg Rausch - Plymouth MN, US
Rob Rabe - Chanhassen MN, US
Jake Klier - Blaine MN, US

International Classification:

G01R 31/28

US Classification:

714731

Abstract:

A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.