Gregory E Alexander

US Patent:

7032097, Apr 18, 2006

Filed:

Apr 24, 2003

Appl. No.:

10/422808

Inventors:

Gregory W. Alexander - Austin TX, US
David S. Levitan - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US
William J. Starke - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711216, 711125, 711137, 711220, 712205, 712207, 712237

Abstract:

A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.

US Patent:

7039768, May 2, 2006

Filed:

Apr 25, 2003

Appl. No.:

10/424487

Inventors:

Gregory William Alexander - Austin TX, US
David Stephen Levitan - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711146, 711125, 711204

Abstract:

A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the I-cache comprises an EA Directory (EA Dir), which includes a series of thread valid bits that are individually assigned to one of the multiple threads. Particular ones of the thread valid bits are set in each EA Dir to indicate when an instruction block the thread is cached within the particular way with which the EA Dir is associated. When a cache line request for a particular thread is received, a cache hit is predicted when the EA of the request matches the EA in the EA Dir and the cache line is selected from the way associated with the EA Dir who has the thread valid bit for that thread set. Early way selection is thus achieved since the way selection only requires a check of the thread valid bits.

US Patent:

7120784, Oct 10, 2006

Filed:

Apr 28, 2003

Appl. No.:

10/425064

Inventors:

Gregory William Alexander - Austin TX, US
Scott Bruce Frommer - Cold Spring NY, US
David Stephen Levitan - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/40
G06F 9/00

US Classification:

712240, 712238, 712239, 712229

Abstract:

Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.

US Patent:

7254678, Aug 7, 2007

Filed:

Mar 17, 2005

Appl. No.:

11/082761

Inventors:

Gregory William Alexander - Austin TX, US
Juan Jose Arevalo - Cedar Park TX, US
Balaram Sinharoy - Poughkeepsie NY, US
Shih-Hsiung Stephen Tung - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711122, 711135

Abstract:

A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, invalidating data for the address in a store-through upper level cache, and placing data returned from the lower level cache into the store-through upper level cache.

US Patent:

7549095, Jun 16, 2009

Filed:

Jun 30, 2008

Appl. No.:

12/165355

Inventors:

Gregory W. Alexander - Pflugerville TX, US
Lee E. Eisen - Round Rock TX, US
Brian W. Thompto - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/00

US Classification:

714709

Abstract:

A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.

US Patent:

7769984, Aug 3, 2010

Filed:

Sep 11, 2008

Appl. No.:

12/208683

Inventors:

Gregory W. Alexander - Pflugerville TX, US
Brian D. Barrick - Pflugerville TX, US
Lee E. Eisen - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30
G06F 9/40
G06F 15/00

US Classification:

712214

Abstract:

A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.

US Patent:

7793086, Sep 7, 2010

Filed:

Sep 10, 2007

Appl. No.:

11/852443

Inventors:

Gregory W. Alexander - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/28

US Classification:

712242

Abstract:

A method for link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function returns. The method comprises establishing a set of physical data structures forming a common pool and an operation control table. Maintaining, within the common pool, a plurality of entries for a plurality of speculative instructions and a plurality of non-speculative instructions. And determining one speculative instruction to be a bad prediction speculative entry, identifying related entries to form a collection, and discarding the collection.

US Patent:

8015362, Sep 6, 2011

Filed:

Feb 15, 2008

Appl. No.:

12/031923

Inventors:

Gregory W. Alexander - Pflugerville TX, US
Christian Jacobi - Schoenaich, DE
Barry W. Krumm - Poughkeepsie NY, US
Chung-Lung Kevin Shum - Wappingers Falls NY, US
Aaron Tsai - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711119, 711123, 711124, 711125, 711126

Abstract:

A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.