Gregory Alexander

US Patent:

20110320789, Dec 29, 2011

Filed:

Jun 23, 2010

Appl. No.:

12/821723

Inventors:

Brian R. Prasky - Wappingers Falls NY, US
Gregory W. Alexander - Pflugerville TX, US
James J. Bonanno - Wappingers Falls NY, US
Aaron Tsai - Poughkeepsie NY, US
Joshua M. Weinberg - Bronx NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/38

US Classification:

712238, 712E09055

Abstract:

A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size along with a branch direction and a branch target of a branch for instructions of a processing pipeline, having a branch target buffer (BTB) predicting the branch target, said branch prediction mechanism storing recently used instructions close to the processor in a local cache, and having a translation look-aside buffer TLB mechanism which tracks the translation of the most recent pages and supports multiple page sizes.

US Patent:

20230054424, Feb 23, 2023

Filed:

Aug 20, 2021

Appl. No.:

17/407248

Inventors:

- Armonk NY, US
Craig R. WALTERS - Highland NY, US
Christian JACOBI - West Park NY, US
Timothy BRONSON - Round Rock TX, US
Gregory William ALEXANDER - Pflugerville TX, US
Hieu T. HUYNH - Austin TX, US
Jason D. KOHL - Austin TX, US
Deanna P. D. BERGER - Hyde Park NY, US
Richard Joseph BRANCIFORTE - Austin TX, US

International Classification:

G06F 12/0891
G06F 12/0895
G06F 12/123

Abstract:

Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

US Patent:

20200371810, Nov 26, 2020

Filed:

May 20, 2019

Appl. No.:

16/416581

Inventors:

- Armonk NY, US
Stefan Payer - Stuttgart, DE
Kerstin Claudia Schelm - Stuttgart, DE
Anthony Saporito - Highland NY, US
Gregory William Alexander - Pflugerville TX, US

International Classification:

G06F 9/38
G06F 9/50

Abstract:

A method of performing instruction scheduling during execution in a processor includes receiving, at an execution unit of the processor, an initial assignment of an assigned execution resource among two or more execution resources to execute an operation. An instruction includes two or more operations. Based on determining that the assigned execution resource is not available, the method also includes determining, at the execution unit, whether another execution resource among the two or more execution resources is available to execute the operation. Based on determining that the other execution resource is available, the method further includes executing the operation with the other execution resource.

US Patent:

20200301706, Sep 24, 2020

Filed:

Mar 19, 2019

Appl. No.:

16/357380

Inventors:

- ARMONK NY, US
Jang-Soo Lee - Poughkeepsie NY, US
Anthony Saporito - Highland NY, US
Chung-Lung K. Shum - Wappingers Falls NY, US
Gregory William Alexander - Pflugerville TX, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.

US Patent:

20200264885, Aug 20, 2020

Filed:

Feb 20, 2019

Appl. No.:

16/280285

Inventors:

- Armonk NY, US
Jonathan Hsieh - Poughkeepsie NY, US
EYAL NAOR - Tel-Aviv, IL
JAMES BONANNO - Wappingers Falls NY, US
Gregory William Alexander - Pflugerville TX, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.