Gregory A Armstrong

US Patent:

53745809, Dec 20, 1994

Filed:

Sep 30, 1993

Appl. No.:

8/129011

Inventors:

David A. Baglee - Houston TX
Robert R. Doering - Plano TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2170
H01L 2700

US Classification:

437 52

Abstract:

A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

US Patent:

51702347, Dec 8, 1992

Filed:

Aug 27, 1991

Appl. No.:

7/758318

Inventors:

David A. Baglee - Houston TX
Robert R. Doering - Plano TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2968
H01L 2702
H01L 2934

US Classification:

257301

Abstract:

A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A word line forms the gate of the access transistor at a hole in the polysilicon field plate.

US Patent:

46777393, Jul 7, 1987

Filed:

Nov 29, 1984

Appl. No.:

6/676351

Inventors:

Robert R. Doering - Plano TX
Michael P. Duane - Houston TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265
H01L 2978
H01L 2704

US Classification:

29576B

Abstract:

A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.

US Patent:

45611700, Dec 31, 1985

Filed:

Jul 2, 1984

Appl. No.:

6/626572

Inventors:

Robert R. Doering - Plano TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21263
H01L 2978
H01L 2704

US Classification:

29571

Abstract:

A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.

US Patent:

46960929, Sep 29, 1987

Filed:

Dec 31, 1985

Appl. No.:

6/815428

Inventors:

Robert R. Doering - Plano TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21263
H01L 2978
H01L 2704

US Classification:

437 5

Abstract:

A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.

US Patent:

20180363416, Dec 20, 2018

Filed:

Jun 14, 2017

Appl. No.:

15/622107

Inventors:

Do Seo Park - Houston TX, US
Marc Samuelson - Houston TX, US
Zhi Yong He - Cypress TX, US
Gregory Armstrong - Houston TX, US
Donavan Holland Brown - Houston TX, US

Assignee:

Baker Hughes Incorporated - Houston TX

International Classification:

E21B 34/08
F16K 15/04
F16K 15/02
F16K 25/00
F16K 25/04
F16K 31/122

Abstract:

A pressurized seat check valve including a flexible frustoconical seat having a back surface configured for exposure to upstream pressure, a closure member in sealable communication with the seat, the closure member being biased into contact with the seat and, in use, the seat being deflected toward the closure member by the exposure to upstream pressure.