Gregory Mark Armstrong

Address:

4544 Wooldrige Ln, Caddo Mills, TX 75135

Phone:

9035275745

VIN:

1GNFC160X7R215378

Make:

CHEVROLET

Model:

SUBURBAN

Year:

2007

US Patent:

55717365, Nov 5, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/478642

Inventors:

James L. Paterson - Richardson TX
Gregory J. Armstrong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218247

US Classification:

437 43

Abstract:

An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

US Patent:

58941622, Apr 13, 1999

Filed:

Oct 26, 1992

Appl. No.:

7/966615

Inventors:

James L. Paterson - Richardson TX
Gregory James Armstrong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29788

US Classification:

257316

Abstract:

An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

US Patent:

46777393, Jul 7, 1987

Filed:

Nov 29, 1984

Appl. No.:

6/676351

Inventors:

Robert R. Doering - Plano TX
Michael P. Duane - Houston TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265
H01L 2978
H01L 2704

US Classification:

29576B

Abstract:

A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.

US Patent:

45611700, Dec 31, 1985

Filed:

Jul 2, 1984

Appl. No.:

6/626572

Inventors:

Robert R. Doering - Plano TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21263
H01L 2978
H01L 2704

US Classification:

29571

Abstract:

A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.

US Patent:

46960929, Sep 29, 1987

Filed:

Dec 31, 1985

Appl. No.:

6/815428

Inventors:

Robert R. Doering - Plano TX
Gregory J. Armstrong - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21263
H01L 2978
H01L 2704

US Classification:

437 5

Abstract:

A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.