Gregory M Armstrong

US Patent:

55717365, Nov 5, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/478642

Inventors:

James L. Paterson - Richardson TX
Gregory J. Armstrong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218247

US Classification:

437 43

Abstract:

An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

US Patent:

58941622, Apr 13, 1999

Filed:

Oct 26, 1992

Appl. No.:

7/966615

Inventors:

James L. Paterson - Richardson TX
Gregory James Armstrong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29788

US Classification:

257316

Abstract:

An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.