Gregory Loren Ebert

US Patent:

7443173, Oct 28, 2008

Filed:

Jun 19, 2006

Appl. No.:

11/455428

Inventors:

Gregory L. Ebert - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 29/26
G01R 23/20
H04B 1/00

US Classification:

324613, 324620, 455 631

Abstract:

Various embodiments for radio frequency (RF) noise cancellation are described. In one embodiment, an apparatus may comprise an RF noise cancellation system arranged to sense platform noise observed by a radio subsystem, create an inverse version of the sensed platform noise, and add the inverse version of the sensed platform noise to a received RF signal to remove the platform noise from the received RF signal. Other embodiments are described and claimed.

US Patent:

7542534, Jun 2, 2009

Filed:

Sep 27, 2005

Appl. No.:

11/237042

Inventors:

Gregory L. Ebert - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 7/00

US Classification:

375354

Abstract:

A method and an apparatus to reduce electromagnetic interference (EMI) have been presented. In one embodiment, the method includes using a first clock signal to create a second clock signal having a fundamental frequency lower than a frequency of the first clock signal, wherein the first clock signal is used to transmit data from a chip within a chip set to an interconnect. The method may further include outputting the second clock signal to the interconnect via a data channel of the chip as a forwarded clock signal. The signal power may be redistributed to lower fundamental frequency to reduce EMI emission from the system. Other embodiments have been claimed and described.

US Patent:

20030060992, Mar 27, 2003

Filed:

Sep 27, 2001

Appl. No.:

09/967169

Inventors:

Gregory Ebert - Portland OR, US

International Classification:

G06F019/00

US Classification:

702/066000

Abstract:

A method is described that involves forming a product waveform by multiplying a positive signal waveform and negative signal waveform. The positive signal waveform and the negative signal waveform are representative of a logical transition within a differential signal. The crossing point voltage of the logical transition within the differential signal is determined by calculating the square root of a maximum of the product waveform.

US Patent:

20170300434, Oct 19, 2017

Filed:

Mar 13, 2017

Appl. No.:

15/457365

Inventors:

- Santa Clara CA, US
Gregory L. Ebert - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/28
G06F 13/42
G06F 13/16
G06F 9/45
G06F 9/52

Abstract:

Methods and apparatus relating to techniques for Electromagnetic Interference (EMI) mitigation on high-speed lanes using false stall are described. In one embodiment, protocol logic determines whether to perform a false stall operation on a lane in response to a determination that no data is to be sent over the lane and that data is being transmitted over the lane. The false stall operation includes sending one or more training symbols (e.g., immediately) after an End Of Burst (EOB) signal over the lane, instead of allowing the lane to stall. Other embodiments are also disclosed.

US Patent:

20150113196, Apr 23, 2015

Filed:

Oct 23, 2013

Appl. No.:

14/125522

Inventors:

Gregory L. Ebert - Portland OR, US

International Classification:

G06F 13/26

US Classification:

710311

Abstract:

Methods and apparatus relating to techniques for Electromagnetic Interference (EMI) mitigation on high-speed lanes using false stall are described. In one embodiment, protocol logic determines whether to perform a false stall operation on a lane in response to a determination that no data is to be sent over the lane and that data is being transmitted over the lane. The false stall operation includes sending one or more training symbols (e.g., immediately) after an End Of Burst (EOB) signal over the lane, instead of allowing the lane to stall. Other embodiments are also disclosed.

US Patent:

20140281085, Sep 18, 2014

Filed:

Mar 15, 2013

Appl. No.:

13/835176

Inventors:

Gregory L. Ebert - Portland OR, US

International Classification:

G06F 9/52

US Classification:

710200

Abstract:

A method, apparatus, and system to recover a clock for a bus comprising: to assign a master lane, to lock non-master lanes to the master lane, to fill the master lane during data inactivity, to idle the non-master lanes during data inactivity, to maintain clock for the master lane, and to recover the clock for the non-master lanes from the master lane. A method, apparatus, and system to transmit and receive serial data with an unsynchronized clock comprising: to transmit data in a bit stream, the data have multiple bit redundancy, to receive the data in the bit stream, to sample a value of the data in the bit stream, to use voting on the value of the data in the bit stream, and to determine a correct logic state for the data from the voting.