Gregory S Green

US Patent:

20100030618, Feb 4, 2010

Filed:

Jul 31, 2008

Appl. No.:

12/221211

Inventors:

Gregory A. Green - Sudbury MA, US
Frank F. Davidson - Sherborn MA, US
Ryder Daniels - Londonderry NH, US

Assignee:

Digitas, Inc. - Boston MA

International Classification:

G06F 17/00
G06F 3/048

US Classification:

705 10, 715719, 700 90

Abstract:

A system and method for visualizing a marketing strategy and its effects on a marketplace are disclosed. Using the system or method, an organization can visualize its marketing strategy in a way that links the original creative intent of the marketing strategy with the marketing strategy's effects upon a marketplace. The method and system enable the organization to evaluate the effectiveness of not only its marketing strategy, but of the creative process that led to the marketing strategy's development. The method and system employ representations of creative aspects of the marketing strategy and representations of effects of the marketing strategy on the marketplace, and present, via a graphical user interface, a user-interactive, creative-aspects-based structure, along with the representations of the effects of the marketing strategy, in a manner enabling interaction with the representations of the creative aspects and the effects on the marketplace.

US Patent:

55862535, Dec 17, 1996

Filed:

Dec 15, 1994

Appl. No.:

8/356561

Inventors:

Gregory M. Green - Boxborough MA
Steven Kohalmi - Newton MA
Karen R. Bricknell - Berlin MA

Assignee:

Stratus Computer - Marlboro MA

International Classification:

G06F 1100

US Classification:

39518506

Abstract:

A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.

US Patent:

56300565, May 13, 1997

Filed:

Sep 20, 1994

Appl. No.:

8/309210

Inventors:

Charles J. Horvath - Concord MA
William I. Leavitt - Grafton MA
Mark D. Tetreault - Northborough MA
Gregory M. Green - Boxborough MA
Peter C. Churchill - Boxborough MA

Assignee:

Stratus Computer, Inc. - Marlboro MA

International Classification:

G06F 1100

US Classification:

39518509

Abstract:

A digital data processing device includes a bus for transmitting signals (e. g. , data and/or address information) between plural functional units (e. g. , a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to the bus complementary portions of like information signals (e. g. , longwords containing data). A fault detection element reads the resultant signal from the bus and compares it with at least portions of the corresponding signals originally generated by the processing sections themselves. If there is discrepancy, the fault-detector signals a fault, e. g. , causing the unit to be taken off-line. By use of a redundant unit, processing can continue for fault-tolerant operation.

US Patent:

58389008, Nov 17, 1998

Filed:

Dec 3, 1996

Appl. No.:

8/759099

Inventors:

Charles J. Horvath - Concord MA
William I. Leavitt - Grafton MA
Mark D. Tetreault - Northborough MA
Gregory M. Green - Boxborough MA
Peter C. Churchill - Boxborough MA

Assignee:

Stratus Computer, Inc. - Marlboro MA

International Classification:

G06F 1100

US Classification:

39518509

Abstract:

A digital data processing device includes a bus for transmitting signals (e. g. , data and/or address information) between plural functional units (e. g. , a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to the bus complementary portions of like information signals (e. g. , longwords containing data). A fault detection element reads the resultant signal from the bus and compares it with at least portions of the corresponding signals originally generated by the processing sections themselves. If there is discrepancy, the fault-detector signals a fault, e. g. , causing the unit to be taken off-line. By use of a redundant unit, processing can continue for fault-tolerant operation.