Gregory J Hamilton

US Patent:

6451181, Sep 17, 2002

Filed:

Mar 2, 1999

Appl. No.:

09/261879

Inventors:

Dean J. Denning - Del Valle TX
Sam S. Garcia - Austin TX
Bradley P. Smith - Austin TX
Daniel J. Loop - Austin TX
Gregory Norman Hamilton - Pflugerville TX
Brian G. Anthony - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

C23C 1434

US Classification:

20419217, 20419215, 20419212, 2041923, 20429806, 438582, 438652, 438653, 438656, 438685, 438698

Abstract:

A method for forming an improved copper inlaid interconnect (FIG. ) begins by performing an RF preclean operation ( ) on the inlaid structure in a chamber ( ). The RF preclean rounds corners ( and ) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces ( ). A tantalum barrier ( ) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer ( ), a copper seed layer ( ) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp ( ) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

US Patent:

20020092763, Jul 18, 2002

Filed:

Feb 22, 2002

Appl. No.:

10/081796

Inventors:

Dean Denning - Del Valle TX, US
Sam Garcia - Austin TX, US
Bradley Smith - Austin TX, US
Daniel Loop - Austin TX, US
Gregory Hamilton - Pflugerville TX, US
Brian Anthony - Austin TX, US

International Classification:

C23C014/32

US Classification:

204/192170, 204/192150, 204/192220

Abstract:

A method for forming an improved copper inlaid interconnect (FIG. ) begins by performing an RF preclean operation () on the inlaid structure in a chamber (). The RF preclean rounds corners (and ) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (). A tantalum barrier () is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (), a copper seed layer () is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp () which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

US Patent:

60939664, Jul 25, 2000

Filed:

Mar 20, 1998

Appl. No.:

9/044852

Inventors:

Ramnath Venkatraman - Austin TX
John Mendonca - Austin TX
Gregory N. Hamilton - Pflugerville TX
Jeffrey T. Wetzel - Austin TX
Tze W. Poon - Sunnyvale CA
Sam S. Garcia - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2972

US Classification:

257751

Abstract:

A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by providing a plurality of refractory metal atoms and a plurality of silicon atoms in the processing chamber. The atoms are ionized by applying a first bias to the atoms to form a plasma. The substrate is then biased by a first stage bias followed by a second stage bias to accelerate the plasma to the substrate to form the copper barrier layer, where the first stage bias is less than the second stage bias. The copper-containing metal is then deposited on the copper barrier layer over the insulating layer and in the opening. The present invention further includes a semiconductor device formed by the above method.