Gregory W Mathews

US Patent:

6381678, Apr 30, 2002

Filed:

Oct 30, 1998

Appl. No.:

09/183519

Inventors:

John Wai Cheong Fu - Saratoga CA
Dean Ahmad Mulla - Ft. Collins CO
Gregory S. Mathews - Santa Clara CA
Stuart E. Sailer - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711137, 711118, 711154, 712237

Abstract:

A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory, and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory. An apparatus includes a memory having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory. The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory.

US Patent:

6405233, Jun 11, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/345717

Inventors:

Gregory S. Mathews - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 750

US Classification:

708670

Abstract:

A technique for receiving a first data from a storage location in which the first data is not stored fully aligned within processor data boundaries for data retrieval. The adder also receives a second data having its alignment adjusted to correspond to the first data and adds the first data and the second data in CPU unaligned format. A carry control circuit coupled to the adder determines which carries are selected for transfer to the next stage for calculating a sum of the two data.

US Patent:

6418521, Jul 9, 2002

Filed:

Dec 23, 1998

Appl. No.:

09/221230

Inventors:

Gregory S. Mathews - Santa Clara CA
Dean A. Mulla - San Jose CA
John Wai Cheong Fu - Saratoga CA
Stuart E. Sailer - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711207, 711122, 711205, 711206

Abstract:

A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB memory having a plurality of entries and a second-level TLB memory operatively coupled to the first level TLB memory. The second-level TLB memory also has a plurality of entries. Entries are placed in the TLB and TLB structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.

US Patent:

6427191, Jul 30, 2002

Filed:

Dec 31, 1998

Appl. No.:

09/224420

Inventors:

John Wai Cheong Fu - Saratoga CA
Dean A. Mulla - San Jose CA
Gregory S. Mathews - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711131, 711154, 711168, 711169

Abstract:

A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The cache design allows two cache requests to be processed simultaneously (dual-ported) and concurrent cache requests to be in-flight (pipelined). The design of the cache allocates a first clock cycle to cache tag and data access and a second cycle is allocated to data manipulation. The memory array circuit design is simplified because the circuits are synchronized to the main processor clock and do not need to use self-timed circuits. The overall logic control scheme is simplified because distinct cycles are allocated to the cache functions.

US Patent:

6567952, May 20, 2003

Filed:

Apr 18, 2000

Appl. No.:

09/551306

Inventors:

Nhon Toai Quach - San Jose CA
Gregory S. Mathews - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714800, 711128, 711144

Abstract:

An apparatus includes a plurality of error detection circuits. Each of the plurality of error detection circuits is coupled to one of a like plurality of ways in a set associative cache memory to receive a tag word and an error detection flag from the coupled way. Each of the plurality of error detection circuits generates a way error signal that is asserted if an error is detected in the tag word of the coupled way. A logical OR circuit is coupled to the plurality of error detection circuits to receive the plurality of way error signals. The logical OR circuit generates a tag error signal that is asserted if at least one of the plurality of way error signals is asserted.

US Patent:

6542966, Apr 1, 2003

Filed:

Jul 16, 1998

Appl. No.:

09/118204

Inventors:

John Crawford - Santa Clara CA
Gautam Doshi - Sunnyvale CA
Stuart E. Sailer - Campbell CA
John Wai Cheong Fu - Saratoga CA
Gregory S. Mathews - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1212

US Classification:

711133

Abstract:

A method is provided for managing temporal and non-temporal data in the same cache structure. The temporal or non-temporal character of data targeted by a cache access is determined, and a cache entry for the data is identified. When the targeted data is temporal, a replacement priority indicator associated with the identified cache entry is updated to reflect the access. When the targeted data is non temporal, the replacement priority indicator associated with the identified cache entry is preserved. The method may also be implemented by employing a first algorithm to update the replacement priority indicator for temporal data and a second, different algorithm to update the replacement priority indicator for non-temporal data.

US Patent:

6560689, May 6, 2003

Filed:

Mar 31, 2000

Appl. No.:

09/541442

Inventors:

Gregory S. Mathews - Santa Clara CA
Gary Hammond - Fort Collins CO

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1214

US Classification:

711204, 711152, 711108, 711220

Abstract:

A prevalidation content addressable memory, CAM, is used to pre-decode a virtual address region extension and enable it for use by a translation look-aside buffer, TLB. The prevalidation CAM removes the region extensions stored in region registers from a serial TLB look-up path.

US Patent:

6625715, Sep 23, 2003

Filed:

Dec 30, 1999

Appl. No.:

09/475607

Inventors:

Gregory S. Mathews - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1204

US Classification:

711207, 711205, 711216

Abstract:

A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to generate a hashed index, the index identifying an entry into two arrays. The first of the two arrays identifies a corresponding physical page address and the other array identifies a corresponding variable page address that in comparison to a variable portion of the virtual address, will indicate whether the entry in the first array has a matching entry. If the first array identifies a matching physical page address, then the physical page address is combined with the offset of the virtual address to yield a physical address translation of the virtual address.