Gregory R Moore

Address:

12114 Whippoorwill Ln, Rockville, MD 20852

VIN:

1G8AJ55F47Z100534

Make:

SATURN

Model:

ION

Year:

2007

US Patent:

7451118, Nov 11, 2008

Filed:

Jul 7, 2004

Appl. No.:

10/884920

Inventors:

Susan McMeen - Burke VA, US
Gregory Moore - Manassas VA, US

Assignee:

United States Postal Service - Washington DC

International Classification:

G06F 9/00

US Classification:

705401, 705 1, 705404, 705406, 705410, 700224, 700226

Abstract:

System and method for creating response pieces. The response piece system authenticates a user, generates a standardized address based on address code information received from the user, and generates a response piece mailpiece based on the standardized address and the information received from the user. In additional embodiments, including an embodiment for prepaid response pieces, the response piece system generates a response piece permit based on permit information received from the user, generates a unique address code based on address code information received from the user, received payment of an identified fee, and generates the response piece mailpiece based on the permit and the unique address code.

US Patent:

53718615, Dec 6, 1994

Filed:

Sep 15, 1992

Appl. No.:

7/945306

Inventors:

Don S. Keener - Boca Raton FL
Gregory J. Moore - Boca Raton FL

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1310

US Classification:

395325

Abstract:

This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer has three interface circuits and a controller processor. The interface circuits control exchange of data among the system central processing unit (CPU), a controller processor, and one or more storage device(s) connected to a SCSI bus. One of the interface circuits includes a least one register for storing data indicative of the content and status of a plurality of sequences of commands ("threads") issued or to be issued to the SCSI device(s).

US Patent:

52993159, Mar 29, 1994

Filed:

Sep 17, 1992

Appl. No.:

7/947013

Inventors:

Arthur L. Chin - Boca Raton FL
Serafin J. Eleazar-Garcia - Boynton Beach FL
Timothy V. Lee - Boca Raton FL
Don S. Keener - Boca Raton FL
Gregory J. Moore - Boca Raton FL
Eric S. Stine - Delray Beach FL

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1314

US Classification:

395250

Abstract:

This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

US Patent:

55509916, Aug 27, 1996

Filed:

Mar 28, 1995

Appl. No.:

8/411916

Inventors:

Don S. Keener - Boca Raton FL
Gregory J. Moore - Boca Raton FL
Richard W. Voorhees - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1310
G06F 1200

US Classification:

395309

Abstract:

This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory. The processor device and storage controller cooperate for exchange of blocks of data between the local processor bus and FIFO memory when the FIFO memory has available one of data to be transferred and space for reception of data and for emptying of the FIFO memory through the local processor bus as necessary.

US Patent:

55242677, Jun 4, 1996

Filed:

Mar 31, 1994

Appl. No.:

8/220793

Inventors:

Arthur L. Chin - Boca Raton FL
Serafin J. E. Garcia - Lake Worth FL
Don S. Keener - Boca Raton FL
Gregory J. Moore - Boca Raton FL
Stephanie P. Payne - Boca Raton FL
Eric S. Stine - Delray Beach FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1320

US Classification:

395823

Abstract:

A digital bus circuit having an Address/Data port select decoder 170 in circuit communication with a Selector 194, a Data Port Buffer/Register 181, and an Address Port register 208. The Selector 194 is in circuit communication with an auto incrementor 216, an auto decrementor 218, and a polling function. The incrementor 216 serves to automatically increment an address present in the Address port register 208. The decrementor 218 serves to automatically decrement an address present in the Address port register 208. The polling function serves to reload the Address port register 208 with the same address. The present invention allows a number of enhanced programming methods which permit input and output operations to be implemented with fewer program code instructions. One of the programming methods disclosed by the present invention is an enhanced method of "polling" a device's internal register by accessing the polling function.

US Patent:

52874761, Feb 15, 1994

Filed:

Jun 7, 1991

Appl. No.:

7/712237

Inventors:

Don S. Keener - Boca Raton FL
Gregory J. Moore - Boca Raton FL

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 900

US Classification:

395425

Abstract:

This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer has a high speed local processor data bus and a storage controller coupled directly to said local processor bus for regulating communications between a processor and storage memory devices. The storage controller has at least one counter for tracking at least one of address and count data for blocks of data being transferred and capable of signalling through the local processor bus the state of the counter, and a bi-stable device interposed between the counter and the local processor bus for enabling delivery to the local processor bus of data representing an initial state of the counter at the beginning of a transfer of blocks of data and for continuing delivery of initial state data throughout a transfer of blocks of data. The counter and bi-stable device cooperate for permitting one of incrementing and decrementing of the counter during transfer of blocks of data while avoiding changes in counter state data delivered to the local processor bus during transfer of blocks of data.

US Patent:

57015147, Dec 23, 1997

Filed:

Apr 1, 1994

Appl. No.:

8/221952

Inventors:

Don Steven Keener - Boca Raton FL
Gregory James Moore - Boca Raton FL

Assignee:

International Business Machines Corporation - Armond NY

International Classification:

G06F 1300
G06F 1314

US Classification:

395834

Abstract:

A computing system with a SCSI controller includes SCSI transmission mode selection apparatus and method to switch the transmission line drivers between transmitting in SCSI 1, SCSI 2 or another mode. The controller selects a maximum data transmission rate compatible with each peripheral device connected to the controller. A user-defined option code is decoded by the controller to provide the user with control over transmission mode options for the drivers in the controller. Based on the data transmission rate and the selected option, the controller selects the SCSI transmission mode to use for each driver type, acknowledge line or data lines.

US Patent:

55863027, Dec 17, 1996

Filed:

Jun 6, 1991

Appl. No.:

7/711245

Inventors:

Don S. Keener - Boca Raton FL
Gregory J. Moore - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395481

Abstract:

This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The storage controller in accordance with this invention has internal volatile memory for transitory storage of data being communicated to coupled volatile memory. It further has control drivers interposed between the internal volatile memory and external volatile memory for controlling communication of data to the external volatile memory, with an enable driver and an enable receiver enchained between the control drivers and a source of signals controlling data communication. The enchained driver and receiver are connected for issuing a write signal to the external volatile memory prior to enablement of data communication through the control drivers and for sustaining a control signal communicated to the control drivers for enabling data communication until after deactivation of the write signal.