Gregory S Starr

US Patent:

6566906, May 20, 2003

Filed:

Sep 18, 2001

Appl. No.:

09/955654

Inventors:

Chiao Kai Hwang - Fremont CA
Gregory Starr - San Jose CA
Martin Langhammer - Poole, GB

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 750

US Classification:

326 38, 326 47, 326 58, 708710

Abstract:

In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

US Patent:

6538470, Mar 25, 2003

Filed:

Sep 18, 2001

Appl. No.:

09/955645

Inventors:

Martin Langhammer - Poole, GB
Gregory Starr - San Jose CA
Chiao Kai Hwang - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 39, 326 40, 708625, 708650, 708505

Abstract:

A programmable logic integrated circuit device (âPLDâ) includes programmable logic and a dedicated (i. e. , at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

US Patent:

6556044, Apr 29, 2003

Filed:

Sep 18, 2001

Appl. No.:

09/955647

Inventors:

Martin Langhammer - Poole, GB
Chiao Kai Hwang - Fremont CA
Gregory Starr - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40, 326 39, 708625, 708523, 714726, 714724, 714725

Abstract:

In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e. g. , subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

US Patent:

6586966, Jul 1, 2003

Filed:

Sep 13, 2001

Appl. No.:

09/952223

Inventors:

Gregory Starr - San Jose CA
Martin Langhammer - Poole, GB
Chiao Kai Hwang - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40, 326 41, 326 37

Abstract:

A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.

US Patent:

6693455, Feb 17, 2004

Filed:

Feb 26, 2003

Appl. No.:

10/377962

Inventors:

Martin Langhammer - Salisbury, GB
Chiao Kai Hwang - Fremont CA
Gregory Starr - San Jose CA

Assignee:

Altera Corporations - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40, 326 39, 708523, 708625, 714724, 714725, 714726

Abstract:

In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e. g. , subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

US Patent:

6714042, Mar 30, 2004

Filed:

Mar 6, 2003

Appl. No.:

10/384905

Inventors:

Chiao Kai Hwang - Fremont CA
Gregory Starr - San Jose CA
Martin Langhammer - Salisbury, GB

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 750

US Classification:

326 38, 326 47, 326 58, 708710

Abstract:

In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

US Patent:

6744277, Jun 1, 2004

Filed:

May 3, 2002

Appl. No.:

10/138685

Inventors:

Wanli Chang - Saratoga CA
Gregory W. Starr - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L 706

US Classification:

326 37, 326 82, 327141, 327144, 327145, 327176, 327291, 327159

Abstract:

A programmable current reference circuit is described. The programmable current reference circuit includes a programmable resistance, where the programmable resistance is programmable to provide one of a plurality of resistances, where each of the plurality of resistances corresponds to one of a plurality of programmable current reference circuit outputs. In one embodiment, the programmable current reference circuit includes a current source coupled to the programmable resistance. In one embodiment, the plurality of programmable current reference circuit outputs includes a plurality of reference currents. A phase locked loop including the programmable current reference circuit is also described.

US Patent:

6771094, Aug 3, 2004

Filed:

Jan 28, 2003

Appl. No.:

10/354440

Inventors:

Martin Langhammer - Poole, GB
Gregory Starr - San Jose CA
Chiao Kai Hwang - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 708625, 708650, 708505

Abstract:

A programmable logic integrated circuit device (âPLDâ) includes programmable logic and a dedicated (i. e. , at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.