Gregory C Starr

US Patent:

6538470, Mar 25, 2003

Filed:

Sep 18, 2001

Appl. No.:

09/955645

Inventors:

Martin Langhammer - Poole, GB
Gregory Starr - San Jose CA
Chiao Kai Hwang - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 39, 326 40, 708625, 708650, 708505

Abstract:

A programmable logic integrated circuit device (âPLDâ) includes programmable logic and a dedicated (i. e. , at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

US Patent:

6586966, Jul 1, 2003

Filed:

Sep 13, 2001

Appl. No.:

09/952223

Inventors:

Gregory Starr - San Jose CA
Martin Langhammer - Poole, GB
Chiao Kai Hwang - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40, 326 41, 326 37

Abstract:

A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.

US Patent:

6744277, Jun 1, 2004

Filed:

May 3, 2002

Appl. No.:

10/138685

Inventors:

Wanli Chang - Saratoga CA
Gregory W. Starr - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L 706

US Classification:

326 37, 326 82, 327141, 327144, 327145, 327176, 327291, 327159

Abstract:

A programmable current reference circuit is described. The programmable current reference circuit includes a programmable resistance, where the programmable resistance is programmable to provide one of a plurality of resistances, where each of the plurality of resistances corresponds to one of a plurality of programmable current reference circuit outputs. In one embodiment, the programmable current reference circuit includes a current source coupled to the programmable resistance. In one embodiment, the plurality of programmable current reference circuit outputs includes a plurality of reference currents. A phase locked loop including the programmable current reference circuit is also described.

US Patent:

6771094, Aug 3, 2004

Filed:

Jan 28, 2003

Appl. No.:

10/354440

Inventors:

Martin Langhammer - Poole, GB
Gregory Starr - San Jose CA
Chiao Kai Hwang - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 708625, 708650, 708505

Abstract:

A programmable logic integrated circuit device (âPLDâ) includes programmable logic and a dedicated (i. e. , at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

US Patent:

6798302, Sep 28, 2004

Filed:

May 3, 2002

Appl. No.:

10/138461

Inventors:

Gregory W. Starr - San Jose CA
Wanli Chang - Saratoga CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03B 2900

US Classification:

331 78, 331 19, 375200

Abstract:

A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

US Patent:

6832173, Dec 14, 2004

Filed:

Jul 30, 2002

Appl. No.:

10/209633

Inventors:

Gregory Starr - San Jose CA
Wanli Chang - Saratoga CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 3500

US Classification:

702106, 327157, 331 16, 375130, 375376

Abstract:

A testing circuit and method for a phase-locked loop allow measurement of leakage currents in the phase-locked loop components. By forcing the output of the phase-frequency detector to a particular state, the charge pump can be disabled. This disables the effect of feedback in the phase-locked loop, and allowing the output frequency to be determined by the voltage on the control voltage node at the time the feedback is disabled. If there is no leakage, the control voltage, and therefore the output frequency, should remain the same as they were at the moment feedback was disabled. Monitoring the output frequency for changes provides an indication of the presence or absence of leakage. Conducting the test using two different charge pump reference currents allows one to detect leakage resulting from charge pump mismatch.

US Patent:

6856180, Feb 15, 2005

Filed:

May 3, 2002

Appl. No.:

10/138595

Inventors:

Gregory W. Starr - San Jose CA, US
Wanli Chang - Saratoga CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L007/06

US Classification:

327147, 327156

Abstract:

A PLL circuit is described. The PLL circuit includes: a feedback loop and a loop filter coupled to the feedback loop, where the loop filter is programmable to provide one of a plurality of bandwidths. In one embodiment, the loop filter is programmable to provide one of a plurality of resistances, each resistance of the plurality of resistances corresponding to one of the plurality of bandwidths. In one embodiment, the feedback loop includes a detector and a signal generator coupled to the detector.

US Patent:

6924678, Aug 2, 2005

Filed:

Oct 21, 2003

Appl. No.:

10/691152

Inventors:

Gregory Starr - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L007/06

US Classification:

327147, 327156

Abstract:

A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections are provided between those components and the remainder of the PLD so that if the PLL is not being used in a particular user design of the PLD, the PLL modular components may be used by other portions of the PLD. Similarly, those connections allow other portions of the PLD to be used in place of one or more of the modular components where more complex or special filtering than can be provided by the modular components is required.