Gregory L Waters

US Patent:

6430527, Aug 6, 2002

Filed:

Aug 26, 1998

Appl. No.:

09/140030

Inventors:

Gregory M. Waters - Groton MA
Larry R. Dennison - Norwood MA
Philip P. Carvey - Bedford MA
William J. Dally - Stanford CA
William F. Mann - Sudbury MA

Assignee:

Avici Systems - N. Billerica MA

International Classification:

G06F 1730

US Classification:

703 3, 707 3, 707 6, 707 7, 370408, 370389, 370413, 709238

Abstract:

Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRALMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

US Patent:

6522632, Feb 18, 2003

Filed:

Jun 25, 1998

Appl. No.:

09/104314

Inventors:

Gregory M. Waters - Groton MA
Larry R. Dennison - Norwood MA
Philip P. Carvey - Bedford MA
William J. Dally - Stanford CA
William F. Mann - Sudbury MA

Assignee:

Avici Systems - N. Billerica MA

International Classification:

H04J 316

US Classification:

370254, 370408

Abstract:

A list of prefix keys, including enclosing prefix key pairs, are stored in leaves of a tree structure. In the leaf nodes, a prefix search key is compared to a set of prefix keys to identify a longest matching prefix. Each leaf node includes a single result pointer to a block of results and a single enclosing pointer to a result in a block of results for another node. Internal nodes which point to subsequent nodes include partitioning nodes and table nodes. In each partitioning node, a prefix search key is compared to a set of prefix keys which point to subsequent nodes through a common pointer and an index. Within each node, a middle prefix key is stored ahead of sets of high and low prefixes.

US Patent:

7130847, Oct 31, 2006

Filed:

Jul 28, 2003

Appl. No.:

10/628312

Inventors:

Gregory M. Waters - Groton MA, US
Larry R. Dennison - Norwood MA, US
Philip P. Carvey - Bedford MA, US
William J. Dally - Stanford CA, US
William F. Mann - Sudbury MA, US

Assignee:

Avici Systems - North Billerica MA

International Classification:

G06F 17/30

US Classification:

707 3, 707 6, 707 7, 707101, 370408, 370413, 709238

Abstract:

Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

US Patent:

7668890, Feb 23, 2010

Filed:

Oct 18, 2006

Appl. No.:

11/582685

Inventors:

Gregory M. Waters - Groton MA, US
Larry R. Dennison - Norwood MA, US
Philip P. Carvey - Bedford MA, US
William J. Dally - Stanford CA, US
William F. Mann - Sudbury MA, US

Assignee:

FutureWei Technologies, Inc. - Plano TX

International Classification:

G06F 17/30

US Classification:

707797, 370389, 370408, 370413

Abstract:

Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

US Patent:

20020152413, Oct 17, 2002

Filed:

Jun 11, 2002

Appl. No.:

10/167689

Inventors:

Gregory Waters - Groton MA, US
Larry Dennison - Norwood MA, US
Philip Carvey - Bedford MA, US
William Dally - Stanford CA, US
William Mann - Sudbury MA, US

International Classification:

H04L001/22
G06F007/00
H02H003/05

US Classification:

714/001000, 707/001000

Abstract:

Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

US Patent:

50705288, Dec 3, 1991

Filed:

Jun 29, 1990

Appl. No.:

7/546629

Inventors:

William R. Hawe - Pepperell MA
Joseph J. Tardo - Acton MA
Charles W. Kaufman - Northboro MA
Amar Gupta - Northboro MA
Barry A. Spinney - Wayland MA
Gregory M. Waters - Boston MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H04L 900

US Classification:

380 48

Abstract:

A method and related cryptographic processing apparatus for handling information packets that are to be cryptographically processed prior to transmission onto a communication network, or that are to be locally cryptographically processed and looped back to a node processor. A special cryptographic preamble is included in each information packet that is to be subject to cryptographic processing. The cryptographic preamble contains an offset value pointing to the starting location of information that is to be processed, and completely defines the type of cryptographic processing to be performed. The cryptographic processor can then perform the processing as specified in the preamble without regard to a specific protocol. If the packet is to be transmitted onto the network, the preamble is stripped from the packet after cryptographic processing, so that the formats of packets transmitted onto the network will be unaffected by the preamble. Cryptographic processing modes include encryption of data for outbound transmission, encryption of a cipher key for loopback to the node processor, encryption or decryption of data for loopback to the node processor, and computation of an integrity check value for loopback to the node processor.

US Patent:

20180006920, Jan 4, 2018

Filed:

Aug 31, 2017

Appl. No.:

15/693045

Inventors:

- Sunnyvale CA, US
Jainendra Kumar - Fremont CA, US
Gregory M. Waters - Groton MA, US

International Classification:

H04L 12/26
H04L 12/801
H04L 12/875

Abstract:

An output circuit, included in a device, may determine counter information associated with a packet provided via an output queue managed by the output circuit. The output circuit may determine that a latency event, associated with the output queue, has occurred. The output circuit may provide the counter information and time of day information associated with the counter information. The output circuit may provide a latency event notification associated with the output queue. An input circuit, included in the device, may receive the latency event notification associated with the output queue. The input circuit may determine performance information associated with an input queue. The input queue may correspond to the output queue and may be managed by the input circuit. The input circuit may provide the performance information associated with the input queue and time of day information associated with the performance information.