Guang Chen

US Patent:

20030103945, Jun 5, 2003

Filed:

Feb 8, 2002

Appl. No.:

10/072830

Inventors:

Dong Chen - Newton MA, US
Xizhong Huang - Framingham MA, US
Guang Chen - Potomac MD, US
Husseini Manji - Rockville MD, US

International Classification:

A61K033/00
A61K038/18
C12N005/08

US Classification:

424/093700, 424/722000, 514/012000, 435/368000

Abstract:

Agents which modulate a bcl family member to control axonal growth and regeneration are described. These bcl modulating agents promote axonal growth and regeneration in the neural cells of a subject. Compositions for promoting axonal cell growth in a subject also are described. The compositions of the present invention include an effective amount of an agent which modulates a bcl family member and in a pharmaceutically acceptable carrier. Other described aspects include packaged drugs for treating a state characterized by diminished potential for axonal growth. The packaged compounds and agents also include instructions for using the agent to promote axonal growth in a subject. An exemplary agent is lithium or a salt thereof.

US Patent:

20050233337, Oct 20, 2005

Filed:

Apr 19, 2004

Appl. No.:

10/828357

Inventors:

Bill Peck - Mountain View CA, US
Eric Leproust - San Jose CA, US
David Adaskin - San Jose CA, US
Guang Chen - San Jose CA, US
William Chesk - San Jose CA, US
Donald Schremp - San Jose CA, US
Stanley Woods - Cupertino CA, US

International Classification:

C12Q001/68
C12M001/34
B05D003/00

US Classification:

435006000, 435287200, 427002110

Abstract:

Methods and devices for fabricating a chemical array are provided. Embodiments include determining a chemical array layout in which each feature in the layout has a size that is chosen based on its composition and fabricating a chemical array according to the chemical array layout. In certain embodiments, at least two features of an array fabricated according to the subject methods are of different sizes. Embodiments also include chemical arrays having features of different sizes, e.g., fabricated according to the subject methods. Also provided are embodiments that include fluid deposition devices capable of fabricating chemical arrays having features of different sizes, e.g., for use in practicing the subject methods. Algorithms present on computer readable mediums for use in practicing the subject methods may also be provided in certain embodiments. Embodiments of the subject invention may also include systems and kits for use in practicing the subject methods.

US Patent:

20220335190, Oct 20, 2022

Filed:

Jul 1, 2022

Appl. No.:

17/856776

Inventors:

Guang Chen - Fremont CA, US
Yuet Li - Fremont CA, US
Archanna Srinivasan - San Jose CA, US

International Classification:

G06F 30/347

Abstract:

Systems or methods of the present disclosure may provide for determining a load line for operation of a programmable logic fabric where the load line is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The load line may be determined using software modeling for the design or configuration. Additionally or alternatively, the load line may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

US Patent:

20210313989, Oct 7, 2021

Filed:

Jun 21, 2021

Appl. No.:

17/353549

Inventors:

- Santa Clara CA, US
Guang Chen - Fremont CA, US
Venu Kondapalli - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19/1778
H03K 21/08

Abstract:

An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.

US Patent:

20210208169, Jul 8, 2021

Filed:

Mar 22, 2021

Appl. No.:

17/209082

Inventors:

- Cambridge MA, US
Guang Chen - Newton MA, US
Qiang Liu - Cambridge MA, US
Brian Wee - Somerville MA, US

International Classification:

G01N 35/00

Abstract:

Embodiments of automated assay processing systems and methods are disclosed. In an example, an assay automation system includes an assay processing tube, a magnet, and a controller. The assay processing tube has a right arm and a left arm, the right arm having an opening for receiving reagent transferred from a reagent tube being held in one of the tube-holding arms of the reagent tube holder, the assay processing tube being driven to rotate. The magnet is driven to move vertically. The controller is configured to control coordinated movements of the assay processing tube and the magnet to perform an assay processing sequence.

US Patent:

20200110101, Apr 9, 2020

Filed:

Oct 2, 2019

Appl. No.:

16/591545

Inventors:

- Cambridge MA, US
Guang Chen - Newton MA, US
Qiang Liu - Cambridge MA, US

International Classification:

G01N 35/00

Abstract:

Embodiments of systems and methods for automated sample handling are disclosed. In an example, a system for automated sample handling includes reaction wells, a magnet, a magnetic manipulator, and a punch. The reaction wells are configured to each hold a reagent and collectively move horizontally. A first reaction well holds magnetic beads, and a second reaction well is partitioned by a seal. The magnet is configured to move vertically and capture the magnetic beads on a bottom surface of the first reaction well when moving to an upper position beneath the first reaction well. The magnetic manipulator is configured to manipulate the magnetic beads and includes a magnetic rod configured to move vertically to be above or in the first reaction well and a sheath below the magnetic rod and configured to move vertically and receive the magnetic rod. The punch is configured to move vertically and break the seal of the second reaction well when moving to a lower position in the second reaction well.

US Patent:

20190044514, Feb 7, 2019

Filed:

Dec 22, 2017

Appl. No.:

15/852814

Inventors:

- Santa Clara CA, US
Guang Chen - Fremont CA, US
Jun Pin Tan - Kepong, MY

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19/003
H03K 19/177
H03K 19/00

Abstract:

An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.