Guanyuan M Yu

US Patent:

7494893, Feb 24, 2009

Filed:

Jan 17, 2007

Appl. No.:

11/654391

Inventors:

Anand Inani - Singapore, SG
Brian E. Stine - Tokyo, JP
Marci Yi-Ting Liao - San Jose CA, US
Senthil Arthanari - San Jose CA, US
Michael V. Williamson - San Jose CA, US
Spencer B. Graves - San Jose CA, US
Guanyuan M. Yu - San Jose CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

H01L 21/76

US Classification:

438424

Abstract:

In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.

US Patent:

20080312875, Dec 18, 2008

Filed:

Jun 12, 2007

Appl. No.:

11/811802

Inventors:

Guanyuan M. Yu - San Jose CA, US
Michael V. Williamson - San Jose CA, US
Spencer B. Graves - San Jose CA, US

International Classification:

G06F 19/00

US Classification:

702182

Abstract:

An integrated circuit (IC) device fabrication process may be monitored by processing product wafers to fabricate product IC devices, collecting process tool data from tools used to fabricate the product IC devices, and testing the product IC devices. To predict and monitor yield, the process tool data collected during processing and the defectivity data from testing the product IC devices may be input to a yield model that also takes into account design information particular to the product devices. The design information may comprise layout attributes of the product devices. The yield model may be generated from a defectivity model created by processing test wafers to fabricate test structures, collecting process tool data from tools used to fabricate the test structures, and testing the test structures. The test structures may have varying layout attributes to cover a design space allowed by design rules for particular product IC devices.

US Patent:

6599132, Jul 29, 2003

Filed:

Nov 30, 1999

Appl. No.:

09/451463

Inventors:

Eric Anthony Perozziello - Half Moon Bay CA
Guanyuan Michael Yu - San Jose CA

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Stanford CA

International Classification:

G01R 3126

US Classification:

437 17, 438 14, 438 18

Abstract:

Currently semiconductor processing and device manufacturing relies heavily on continued scaling of critical dimensions for cost reduction and performance enhancement. In order to continue this scaling below 0. 1 micron with acceptable manufacturing yields, reliable measurement of electrical charge distribution and the placement of dopants is essential, yet no conventional technique exists to obtain distortion-free cross-sectional images. An aspect of the invention relates to a technique for forming a precisely-located, substantially atomically smooth cross-section of a crystalline sample suitable for Scanning Capacitance Microscopy analysis. Another aspect of the invention provides a method for deconvolving Scanning Capacitance raw data into an accurate representation of electrical carrier distributions suitable for the higher resolution attainable with the new sample preparation technique.