Guo Z Chen

US Patent:

20220217098, Jul 7, 2022

Filed:

Apr 2, 2020

Appl. No.:

17/606715

Inventors:

- Redmond WA, US
Ran Shu - Redmond WA, US
Lei Qu - Redmond WA, US
Peng Chen - Redmond WA, US
Yongqiang Xiong - Beijing, CN
Guo Chen - Redmond WA, US

International Classification:

H04L 49/102
H04L 49/9005
H04L 49/90
H04L 67/1097

Abstract:

In accordance with implementations of the subject matter described herein, there is provided a solution for streaming communication between devices. In this solution, a memory of a first device comprising a ring buffer is allocated to be dedicated for storing a data stream of an application to be transmitted to a second electronic device. The application of the first device writes data to be transmitted into the ring buffer, to form a portion of the first data stream, and a write pointer of the ring buffer is thus updated. A portion of data is read based on a source memory address from the ring buffer via the interface device. The interface device also transmits the data portion to a second device. The read data portion is stored in a dedicated ring buffer of the memory. In accordance with the solution, an efficient streaming communication interface is provided between devices.

US Patent:

20220206979, Jun 30, 2022

Filed:

Dec 23, 2021

Appl. No.:

17/560524

Inventors:

- Redmond WA, US
Ran SHU - Redmond WA, US
Guo CHEN - Redmond WA, US
Yongqiang XIONG - Redmond WA, US
Jiansong ZHANG - Redmond WA, US
Ningyi XU - Redmond WA, US

Assignee:

MICROSOFT TECHNOLOGY LICENSING, LLC - Redmond WA

International Classification:

G06F 13/38
G06F 13/12
G06F 21/76
H04L 65/1069
H04L 69/12

Abstract:

According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

US Patent:

20200167302, May 28, 2020

Filed:

Apr 24, 2018

Appl. No.:

16/615053

Inventors:

- Redmond WA, US
Ran SHU - Redmond WA, US
Guo CHEN - Redmond WA, US
Yongqiang XIONG - Redmond WA, US
Jiansong ZHANG - Redmond WA, US
Ningyi XU - Redmond WA, US

Assignee:

MICROSOFT TECHNOLOGY LICENSING, LLC - Redmond WA

International Classification:

G06F 13/38
G06F 21/76
G06F 13/12
H04L 29/06

Abstract:

According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

US Patent:

20200117630, Apr 16, 2020

Filed:

Apr 25, 2018

Appl. No.:

16/616301

Inventors:

- Redmond WA, US
Ran SHU - Redmond WA, US
Guo CHEN - Redmond WA, US
Yongqiang XIONG - Redmond WA, US
Jiansong ZHANG - Redmond WA, US
Ningyi XU - Redmond WA, US

Assignee:

MICROSOFT TECHNOLOGY LICENSING, LLC - Redmond WA

International Classification:

G06F 13/40
H04L 12/741
H04L 29/06
H04L 12/725

Abstract:

The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.