Haiyan C Yu Gong from Princeton, NJ, age 50

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Sram Core Cell Design With Write Assist
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US Patent:

20140313817, Oct 23, 2014
Filed:

Apr 18, 2013
Appl. No.:

13/865281
Inventors:

- Santa Clara CA, US
Ge YANG - Dublin CA, US
Fei SONG - Santa Clara CA, US
Xi ZHANG - San Jose CA, US
Haiyan GONG - San Jose CA, US
Assignee:

NVIDIA CORPORATION - Santa Clara CA
International Classification:

G11C 11/413
US Classification:

365154
Abstract:

A static random access memory (SRAM) cell is disclosed. The SRAM cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.

Mitigating External Influences On Long Signal Lines
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US Patent:

20140169108, Jun 19, 2014
Filed:

Dec 14, 2012
Appl. No.:

13/715991
Inventors:

- Santa Clara CA, US
Xi Zhang - San Jose CA, US
Jiani Yu - Fremont CA, US
Haiyan Gong - San Jose CA, US
Assignee:

NVIDIA CORPORATION - Santa Clara CA
International Classification:

G11C 7/00
US Classification:

36518911
Abstract:

Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Low Power, Single-Rail Level Shifters Employing Power Down Signal From Output Power Domain And A Method Of Converting A Data Signal Between Power Domains
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US Patent:

20140084984, Mar 27, 2014
Filed:

Sep 25, 2012
Appl. No.:

13/626100
Inventors:

- Santa Clara CA, US
Ge Yang - Dublin CA, US
Xi Zhang - San Jose CA, US
Jiani Yu - Fremont CA, US
Haiyan Gong - San Jose CA, US
Assignee:

NVIDIA CORPORATION - Santa Clara CA
International Classification:

H03L 5/00
US Classification:

327333
Abstract:

Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.