Han C Cho

US Patent:

20150144154, May 28, 2015

Filed:

Oct 24, 2014

Appl. No.:

14/522864

Inventors:

- Santa Clara CA, US
Sang Wook KIM - Palo Alto CA, US
Joo Won HAN - Santa Clara CA, US
Han Soo CHO - San Jose CA, US

International Classification:

B08B 7/00

US Classification:

134 11, 134 30

Abstract:

Embodiments of the disclosure generally relate to methods of removing etch by-products from the plasma processing chamber using carbon monoxide or carbon dioxide. In one embodiment, a method for dry cleaning a processing chamber includes exposing a chamber component disposed within the processing chamber in absence of a substrate disposed therein to a first cleaning gas mixture comprising carbon monoxide or carbon dioxide, wherein a portion of the chamber component has a film layer or residues deposited thereon, and the film layer or residues comprises a refractory metal and/or a metal silicide.

US Patent:

20150031187, Jan 29, 2015

Filed:

Jul 23, 2013

Appl. No.:

13/948269

Inventors:

Joo Won Han - Santa Clara CA, US
Kee Young CHO - San Jose CA, US
Han Sao CHO - San Jose CA, US
Sang Wook KIM - Palo Alto CA, US
Anisul H. KHAN - Santa Clara CA, US

Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA

International Classification:

H01L 21/762

US Classification:

438404

Abstract:

Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Clgas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.

US Patent:

20150004796, Jan 1, 2015

Filed:

Jun 24, 2014

Appl. No.:

14/313246

Inventors:

- Santa Clara CA, US
HAN SOO CHO - San Jose CA, US
JOO WON HAN - Santa Clara CA, US
KEE YOUNG CHO - San Jose CA, US
KUAN-TING LIU - Stanford CA, US
ANISUL KHAN - Santa Clara CA, US

International Classification:

H01L 21/3065
H01L 21/308

US Classification:

438719, 438710

Abstract:

In some embodiments, a method of forming a three dimensional NAND structure atop a substrate may include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers; providing a process gas comprising sulfur hexafluoride (SF), carbon tetrafluoride (CF), and oxygen (O) to the process chamber; providing an RF power of about 4 kW to about 6 kW to an RF coil to ignite the process gas to form a plasma; and etching through a desired number of the alternating layers to form a feature of a NAND structure.