Hang T Nguyen

US Patent:

6615366, Sep 2, 2003

Filed:

Dec 21, 1999

Appl. No.:

09/470096

Inventors:

Edward T. Grochowski - San Jose CA
William Rash - Saratoga CA
Nhon Quach - San Jose CA
Hang Nguyen - Tempe AZ
Andres Rabago - Tempe AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 10, 712 1, 712 43

Abstract:

A processor is provided having dual execution cores that may be switched between high reliability and high performance execution modes dynamically, according to the type of code segment to be executed. When the processor is in high performance mode, the dual execution cores operate in lock step on identical instructions, and the execution results generated by each execution core are compared to detect any errors. In high performance monde, the dual execution cores operate independently.

US Patent:

6763437, Jul 13, 2004

Filed:

Sep 7, 2000

Appl. No.:

09/656529

Inventors:

Trung Nguyen - San Jose CA
Hang Nguyen - Fremont CA
John W. Brooks - San Jose CA
Parminder K. Gill - Fremont CA

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

G06F 1336

US Classification:

711147, 151158, 151112

Abstract:

A method and system of providing access to a shared memory interconnected to a first controller and a second controller via a bus, the bus having control signals associated therewith for data transfer control and communication between the first and the second controllers. The second controller transmits an access request to the first controller for control of the bus to access the memory. The first controller selectively grants the access request and transmits an acknowledge to the second controller; and upon receiving the acknowledge, the second controller accesses the memory for data transfer. The first controller has a first priority for accessing the memory, and the second controller has a second priority for accessing the memory, the second priority being lower than the first priority such that upon request the first controller selectively grants control of the bus to the second controller for memory access, otherwise the first controller maintains control of the bus for memory access. In one embodiment, the second controller transmits an access request to the first controller for control of the bus to access the memory; and in response, the first controller selectively grants the access request and transmits an acknowledge to the second controller. Each of the controllers relinquishes control of the bus by placing the bus in tristate, wherein the relinquishing controller stops driving the bus.

US Patent:

54466121, Aug 29, 1995

Filed:

Mar 22, 1994

Appl. No.:

8/216222

Inventors:

Arnold O. Thornton - San Jose CA
Hang T. Nguyen - San Jose CA
Greg N. Nguyen - San Jose CA
Don P. Williams - San Jose CA

Assignee:

Areal Technology, Inc. - San Jose CA

International Classification:

G11B 548

US Classification:

360104

Abstract:

A head suspension assembly for a hard disk drive data storage device which prevents contact between the head portion of the mechanism and the surface of the data storage media. An arm member includes a head assembly secured to one end and a bushing at the other end for engaging a rotatable positioning shaft. The arm member applies a resilient beam loading force to urge the arm member away from the media, and includes an aerodynamic airfoil that interacts with the air flow adjacent to the media surface to oppose the beam loading force and move the arm member toward the media to a proper flying height. When the disk is spinning, the negative lift of the airfoil opposes the resilient loading of the arm member and urges the arm member closer to the surface of the rotating media. As the head approaches the rotating surface, the positive lift of the air bearing counterbalances the negative lift from the airfoil such that a dynamic equilibrium is established at a predetermined flying height. The assembly intrinsically prevents head-to-disk stiction and may minimize head crashes that are normally caused by excessive preload.

US Patent:

59639776, Oct 5, 1999

Filed:

Oct 9, 1997

Appl. No.:

8/947213

Inventors:

Clifford M. Gold - Fremont CA
Hang D. Nguyen - Fremont CA
George Li - Santa Clara CA
Minnie Uppuluri - San Jose CA
Hoa Luong - Fremont CA
Steve Paul - Santa Cruz CA
Bryan Mee - San Jose CA
Trinh Bui - San Jose CA

Assignee:

Quantum Corporation - Milpitas CA

International Classification:

G06F 1200

US Classification:

711156

Abstract:

A method of coordinating access to a data buffer including a plurality of data blocks, using a buffer list with a plurality of entries corresponding to the data blocks. Each buffer list entry includes: (i) a status code for indicating the status of data in the corresponding data block, and (ii) a partial address common to both the next buffer list entry and a data block corresponding to said next buffer list entry. A status code is selected from a cyclical set of sequential status codes having a period of N, the status codes sequentially, and alternately, representing the most recent history of a data block, including: (i) full status, indicating data in the data block has been retrieved from the storage device or is to be stored to the storage device, or (ii) empty status, indicating data transferred out of the data block to a host or to the storage device. A store flag maintains a status code representing empty status, and a retrieve flag maintains a status code representing full status. When storing data into the data buffer, locating a desired buffer list entry list with an empty status code by traversing the buffer list, calculating the address of each entry using the partial address in the previous entry, until the desired entry is found.

US Patent:

49146521, Apr 3, 1990

Filed:

Aug 1, 1988

Appl. No.:

7/226610

Inventors:

Hang Diem Nguyen - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04J 302

US Classification:

370 855

Abstract:

A method is provided for use in a Token ring network including a plurality of stations serially connected by a transmission medium so as to form a closed loop on which packets of data are circulated, wherein each respective station includes a media access controller and a buffer memory, the method including the steps of transferring data of a respective packet from a media access controller to a buffer memory; storing the data in a sequence of contiguous memory locations in the buffer memory; in the course of the step of transferring the data, generating status information for the data; after said step of storing the data, storing the status information in the buffer memory contiguously with the stored data at the beginning of the sequence of memory locations in which the data are stored.