Hanh Duc Hoang

US Patent:

7464287, Dec 9, 2008

Filed:

Mar 31, 2004

Appl. No.:

10/815903

Inventors:

Debendra Das Sharma - Santa Clara CA, US
Gurushankar Rajamani - Sunnyvale CA, US
Hanh Hoang - Bay Point CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 5/06
G06F 17/50
G06F 7/62

US Classification:

713600, 703 13, 703 14, 703 15

Abstract:

Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

US Patent:

7770051, Aug 3, 2010

Filed:

Sep 22, 2008

Appl. No.:

12/235532

Inventors:

Debendra Das Sharma - Santa Clara CA, US
Gurushankar Rajamani - Sunnyvale CA, US
Hanh Hoang - Bay Point CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/04
G06F 17/50

US Classification:

713600, 703 13, 703 14, 703 15

Abstract:

Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

US Patent:

7836352, Nov 16, 2010

Filed:

Jun 30, 2006

Appl. No.:

11/479417

Inventors:

Debendra Das Sharma - Santa Clara CA, US
Surena Neshvad - Hillsboro OR, US
Guru Rajamani - Sunnyvale CA, US
Hanh Hoang - Sunnyvale CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 44, 714 43, 714801, 714704, 706 7

Abstract:

A method and apparatus is described herein for tracking errors for one of a plurality of lanes in a link, tracking errors for the link, and in the case of a root complex, tracking error correction messages. This information is used to determine the suitability for use of a lane and to determine if correction action is needed. In one embodiment, this method and apparatus is used with PCI Express interconnects.

US Patent:

8209563, Jun 26, 2012

Filed:

Apr 8, 2010

Appl. No.:

12/756998

Inventors:

Debendra Das Sharma - Santa Clara CA, US
Gurushankar Rajamani - Sunnyvale CA, US
Hanh Hoang - Bay Point CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/04
G06F 17/50
G06G 7/62

US Classification:

713600, 703 13, 703 14, 703 15

Abstract:

Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

US Patent:

20200143088, May 7, 2020

Filed:

Sep 27, 2018

Appl. No.:

16/144705

Inventors:

- San Jose CA, US
Anujan Varma - Cupertino CA, US
Chuan Cheng Pan - San Jose CA, US
Patrick C. McCarthy - San Francisco CA, US
Hanh Hoang - Hayward CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 21/72
H04L 9/06

Abstract:

A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit. The encryption circuit encrypts the plaintext input packet based on the first cryptographic parameters, and the decryption circuit decrypts the ciphertext input packet based on the second cryptographic parameters.

US Patent:

20190243781, Aug 8, 2019

Filed:

Feb 8, 2018

Appl. No.:

15/892266

Inventors:

- San Jose CA, US
Darren Jue - Sunnyvale CA, US
Tao Yu - Campbell CA, US
John West - Erie CO, US
Hanh Hoang - Hayward CA, US
Ravi Sunkavalli - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 12/1081

Abstract:

Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.