Hari V Mallela

US Patent:

20100204940, Aug 12, 2010

Filed:

Feb 9, 2009

Appl. No.:

12/367564

Inventors:

Gasner J. Barthold - Fishkill NY, US
Hari V. Mallela - Poughquag NY, US
Yunsheng Song - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/06
G06F 17/30
G06F 19/00

US Classification:

702 82, 707E17044, 707E17014, 707E17046

Abstract:

According to an embodiment of the present invention is to provide methods to evaluate the impact of scrapped wafers on the remaining wafers in a lot by using scrap codes and statistical models. An embodiment of the present invention provides a method to obtain a baseline lot population by using cluster analysis model and functional limited yields. The functional limited yields may be for example chain limited yield, dc limited yield, or ac abist limited yield. By utilizing statistical modeling it is possible to determine which failures have an impact on the lot yield and require rework for the lot. In addition by monitoring the impact of failures, it is possible to determine if corrective actions need to be taken for lots that passed through a process prior to correction of the fault.

US Patent:

20200312912, Oct 1, 2020

Filed:

Mar 28, 2019

Appl. No.:

16/368065

Inventors:

- ARMONK NY, US
TAKASHI ANDO - Tuckahoe NY, US
HARI MALLELA - Poughquag NY, US
Li-Wen Hung - Mahopac NY, US

International Classification:

H01L 27/24
H01L 45/00
G11C 13/00

Abstract:

A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.

US Patent:

20200143233, May 7, 2020

Filed:

Nov 2, 2018

Appl. No.:

16/178627

Inventors:

- Armonk NY, US
Reinaldo Vega - Mahopac NY, US
Hari Mallela - Poughquag NY, US

International Classification:

G06N 3/063
G06N 3/04
G06N 3/08

Abstract:

Provided are embodiments of a multi-task learning system with hardware acceleration that includes a resistive random access memory crossbar array. Aspects of the invention includes an input layer that has one or more input layer nodes for performing one or more tasks of the multi-task learning system, a hidden layer that has one or more hidden layer nodes, and a shared hidden layer that has one or more shared hidden layer nodes which represent a parameter, wherein the shared hidden layer nodes are coupled to each of the one or more hidden layer nodes of the hidden layer.

US Patent:

20200051979, Feb 13, 2020

Filed:

Aug 13, 2018

Appl. No.:

16/101659

Inventors:

- Armonk NY, US
Reinaldo Vega - Mahopac NY, US
Choonghyun Lee - Rensselaer NY, US
Hari Mallela - Poughquag NY, US
Li-Wen Hung - Mahopac NY, US

International Classification:

H01L 27/092
H01L 21/8238
H01L 21/28
H01L 29/51
H01L 29/423
H01L 29/49

Abstract:

Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.

US Patent:

20190319006, Oct 17, 2019

Filed:

Apr 11, 2018

Appl. No.:

15/950239

Inventors:

- ARMONK NY, US
Reinaldo VEGA - Mahopac NY, US
Hari MALLELA - Poughquag NY, US

International Classification:

H01L 23/00

Abstract:

A technique relates to a semiconductor device. First nanowires are formed on a first substrate, the first nanowires being electrically coupled to one or more first electrical sites on the first substrate. Second nanowires are formed on a second substrate, the second nanowires being electrically coupled to one or more second electrical sites on the second substrate. The first nanowires and the second nanowires are electrically coupled such that the one or more first electrical sites are electrically coupled to the one or more second electrical sites.

US Patent:

20180240892, Aug 23, 2018

Filed:

Feb 21, 2017

Appl. No.:

15/438383

Inventors:

- Armonk NY, US
Hari V. Mallela - Poughquag NY, US
Hiroyuki Miyazoe - White Plains NY, US
Reinaldo A. Vega - Mahopac NY, US
Rajasekhar Venigalla - Hopewell Junction NY, US

International Classification:

H01L 29/66
H01L 29/78
H01L 21/308
H01L 29/161

Abstract:

Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.

US Patent:

20180240894, Aug 23, 2018

Filed:

Jan 19, 2018

Appl. No.:

15/875619

Inventors:

- Armonk NY, US
Hari V. MALLELA - Poughquag NY, US
Hiroyuki MIYAZOE - White Plains NY, US
Reinaldo A. VEGA - Mahopac NY, US
Rajasekhar VENIGALLA - Hopewell Junction NY, US

International Classification:

H01L 29/66
H01L 29/78
H01L 21/308
H01L 29/161

Abstract:

Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.

US Patent:

20160329251, Nov 10, 2016

Filed:

May 7, 2015

Appl. No.:

14/706288

Inventors:

- Armonk NY, US
Sameer H. Jain - Beacon NY, US
Unoh Kwon - Fishkill NY, US
Zhengwen Li - Scarsdale NY, US
Hari V. Mallela - Poughquag NY, US
Ayse M. Ozbek - Fishkill NY, US
Cung D. Tran - Newburgh NY, US
Reinaldo A. Vega - Wappingers Falls NY, US
Richard S. Wise - Los Altos CA, US

International Classification:

H01L 21/8234
H01L 27/088

Abstract:

A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing minor sides of the trench region include a spacer layer, but the central portion of the trench region is substantially free from the spacer layer. The spacer layer is formed using an angled gas cluster ion beam.