He E Lin

US Patent:

56867450, Nov 11, 1997

Filed:

Jun 19, 1995

Appl. No.:

8/492431

Inventors:

He Lin - Dallas TX
Alex Ignatiev - Houston TX
Nai Juan Wu - Houston TX

Assignee:

University of Houston - Houston TX

International Classification:

H01L 2976
H01L 2994
H01L 31062
H01L 31113

US Classification:

257295

Abstract:

A three-terminal non-volatile ferroelectric/superconductor thin film field effect transistor (FsuFET). The FSuFET is used as a non-volatile memory storage device that provides two static states and four transient states. The FSuFET includes a superconducting film epitaxially grown on a substrate layer. A ferroelectric thin film is then epitaxially grown on the superconducting layer to form the gate of the FSuFET. A drain electrode and a source electrode are then contacted to the superconducting film on either side of the ferroelectric gate. In static mode, the two polarization states of the ferroelectric gate correspond to the binary "0" and "1" states, which are switched by applying a voltage pulse of sufficient magnitude. In transient mode, the four states depend upon the polarization state of the ferroelectric gate and the conductive state (superconducting or non-superconducting) of the drain-source channel. The four states are generated at the drain of the FSuFET and consist of a positive, high pulse; a positive, low pulse; a negative, high pulse; and a negative, low pulse.

US Patent:

20200161415, May 21, 2020

Filed:

Jan 28, 2020

Appl. No.:

16/774014

Inventors:

- Dallas TX, US
ZHIPENG FENG - CHENGDU, CN
HE LIN - FRISCO TX, US
YUNLONG LIU - CHENGDU, CN
MANOJ JAIN - PLANO TX, US

International Classification:

H01L 49/02
H01L 21/768
H01L 21/02
H01L 21/3215
H01L 21/3213
H01L 23/495
H01L 23/00
H01L 21/3205
H01L 25/18
H01L 21/306

Abstract:

A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

US Patent:

20190229074, Jul 25, 2019

Filed:

Apr 1, 2019

Appl. No.:

16/372117

Inventors:

- DALLAS TX, US
He Lin - Frisco TX, US

International Classification:

H01L 23/60
H01L 29/868
H01L 27/02
H01L 29/15

Abstract:

In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.

US Patent:

20190229181, Jul 25, 2019

Filed:

Jul 6, 2018

Appl. No.:

16/028862

Inventors:

- Dallas TX, US
ZHIPENG FENG - CHENGDU, CN
HE LIN - FRISCO TX, US
YUNLONG LIU - CHENGDU, CN
MANOJ JAIN - PLANO TX, US

International Classification:

H01L 49/02
H01L 21/306
H01L 21/768
H01L 21/02
H01L 21/3215
H01L 21/3213
H01L 23/495
H01L 23/00
H01L 21/3205
H01L 25/18

Abstract:

A trench capacitor includes a plurality of trenches in a doped semiconductor surface layer of a substrate. At least one dielectric layer lines a surface of the plurality of trenches. A second polysilicon layer that is doped is on a first polysilicon layer that is on the dielectric layer which fills the plurality of trenches. The second polysilicon layer has a higher doping level as compared to the first polysilicon layer.