Heather T Hanson

US Patent:

6950904, Sep 27, 2005

Filed:

Jun 25, 2002

Appl. No.:

10/180700

Inventors:

Todd D. Erdner - Austin TX, US
Bradley G. Burgess - Austin TX, US
Heather L. Hanson - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/08

US Classification:

711136, 711134

Abstract:

A cache way replacement technique to identify and replace a least-recently used cache way. A cache way replacement technique in which a least-recently used cache way is identified and replaced, such that the replacement of cache ways over time is substantially evenly distributed among a set of cache ways in a cache memory. A least-recently used cache way is identified in a cache memory having a non-binary number of cache ways.

US Patent:

7890831, Feb 15, 2011

Filed:

Jun 10, 2008

Appl. No.:

12/136458

Inventors:

Michael L. Choate - Round Rock TX, US
Mark D. Nicol - Austin TX, US
Heather L. Hanson - Austin TX, US
Michael J. Borsch - Austin TX, US
Arthur M. Ryan - Round Rock TX, US
Chandrakant Pandya - Pflugerville TX, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

G06F 11/00
G01R 31/28

US Classification:

714742, 714 10, 714 47, 714736

Abstract:

A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.

US Patent:

8250395, Aug 21, 2012

Filed:

Nov 12, 2009

Appl. No.:

12/616833

Inventors:

John B. Carter - Austin TX, US
Heather L. Hanson - Austin TX, US
Karthick Rajamani - Austin TX, US
Todd J. Rosedahl - Zumbrota MN, US
Malcolm S. Ware - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00
G06F 1/32
G06F 1/12
G06F 15/16
G06F 12/00
G06F 13/24
G06F 15/00
G06F 9/46

US Classification:

713322, 713320, 713375, 709248, 710240, 710260, 712 23, 712215, 718102

Abstract:

A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors.

US Patent:

8261112, Sep 4, 2012

Filed:

Dec 8, 2008

Appl. No.:

12/330284

Inventors:

John B. Carter - Austin TX, US
Heather L. Hanson - Austin TX, US
Karthick Rajamani - Austin TX, US
Malcolm S. Ware - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/32
G06F 1/26
G06F 1/08

US Classification:

713320, 713300, 713310, 713321, 713322, 713324, 713330, 713340, 700 29, 702 75

Abstract:

A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.

US Patent:

8276012, Sep 25, 2012

Filed:

Jun 30, 2009

Appl. No.:

12/495188

Inventors:

Heather L. Hanson - Austin TX, US
Charles R. Lefurgy - Austin TX, US
Karthick Rajamani - Austin TX, US
Malcolm S. Ware - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26

US Classification:

713320, 718100

Abstract:

A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

US Patent:

8381004, Feb 19, 2013

Filed:

May 26, 2010

Appl. No.:

12/787842

Inventors:

Elmootazbellah N. Elnozahy - Austin TX, US
Heather L. Hanson - Austin TX, US
Malcolm S. Ware - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/32

US Classification:

713321, 713320, 713322, 713323, 718105

Abstract:

A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.

US Patent:

8429433, Apr 23, 2013

Filed:

Jan 15, 2010

Appl. No.:

12/688214

Inventors:

John B. Carter - Austin TX, US
Heather L. Hanson - Austin TX, US
Karthick Rajamani - Austin TX, US
Malcolm S. Ware - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00
G06F 1/26
G05D 3/12
G01R 21/00
G01R 19/00

US Classification:

713300, 713320, 700295, 702 60, 702 64

Abstract:

A mechanism is provided for dynamically power capping one or more units. A power capping mechanism sets a counter value corresponding to an initial energy budget assigned to a unit for a given interval. Responsive to the unit receiving an operation to perform during the given interval, the power capping mechanism decrements the counter value by a decrement value. Responsive to the given interval expiring, the power capping mechanism sends the counter value to a power control loop in the data processing system, receives a new energy budget from the power control loop, and resets the counter value to a value corresponding to the new energy budget assigned to the unit for a next interval.

US Patent:

8510749, Aug 13, 2013

Filed:

May 27, 2010

Appl. No.:

12/789015

Inventors:

Elmootazbellah Nabil Elnozahy - Austin TX, US
Heather Lynn Hanson - Austin TX, US
James Lyle Peterson - Austin TX, US
Malcolm Scott Ware - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 9/46

US Classification:

719310, 718100

Abstract:

A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.