Hee Bok Lee

US Patent:

8170506, May 1, 2012

Filed:

Jul 29, 2008

Appl. No.:

12/181904

Inventors:

Bahman Ahrari - Los Gatos CA, US
Hee Choul Lee - San Jose CA, US
Jin-Su Ko - San Jose CA, US
Sang Oh Lee - Cupertino CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04B 1/04
H04B 17/00

US Classification:

4551142, 4551151, 455 6713

Abstract:

Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction.

US Patent:

8266379, Sep 11, 2012

Filed:

Jun 2, 2003

Appl. No.:

10/453226

Inventors:

Hee Choul Lee - Cupertino CA, US

Assignee:

Infineon Technologies AG

International Classification:

G06F 12/06

US Classification:

711118, 711E12039

Abstract:

A multithreaded processor includes multiple level-1 program caches and multiple level-1 data caches to decrease the likelihood of cache misses after thread switches. By using multiple level-1 caches, execution of a first thread does not cause instructions or data cached for a second thread to be replaced. Thus, when the second thread is being executed the occurrence of cache misses is reduced.

US Patent:

8514953, Aug 20, 2013

Filed:

Nov 6, 2007

Appl. No.:

11/935903

Inventors:

Hee Choul Lee - San Jose CA, US
Chan Hong Park - San Jose CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04L 27/28

US Classification:

375260

Abstract:

Techniques for writing to registers associated with MIMO signal paths are disclosed. In an embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.