Hehching H Li

US Patent:

6754867, Jun 22, 2004

Filed:

Dec 28, 2000

Appl. No.:

09/750199

Inventors:

Ajay Ojha - Beaverton OR
Hehching Harry Li - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714739, 438 17, 326 16

Abstract:

A novel apparatus and methods provide the capability to structural test device input/output pins which are not connected to an external tester during the testing process. The method does not require a new Design For Test logic block, but rather, the method modifies existing registers on the chip to function as a (Pseudo Random Pattern Generator) PRPG and a MISR (Multiple Input Signature Register). The PRPG generates input patterns. The MISR generates an output signature. PRPG and MISR are both based on LFSR (Linear Feedback Shift Register). This allows running a random pattern generated by the PRPG, testing at-speed a path from the PRPG through the I/O logic circuitry interfacing to core logic, and storing a signature pattern in the MISR. The testing will take place at native speed of the device and no connection to the pins is required externally.

US Patent:

7437531, Oct 14, 2008

Filed:

Sep 30, 2004

Appl. No.:

10/955420

Inventors:

Michael Spica - Hillsboro OR, US
Hehching Harry Li - Portland OR, US
Md Rezwanur Rahman - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/02
G11C 29/18
G01R 31/28

US Classification:

711217, 714718, 714728

Abstract:

Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.

US Patent:

63112957, Oct 30, 2001

Filed:

Jun 14, 1996

Appl. No.:

8/663969

Inventors:

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
David Ming-Whei Wu - Spring TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 305
H03K 19003

US Classification:

714 55

Abstract:

The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ("PLL") circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.

US Patent:

59173564, Jun 29, 1999

Filed:

Sep 11, 1995

Appl. No.:

8/526395

Inventors:

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 300

US Classification:

327236

Abstract:

A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

US Patent:

55816991, Dec 3, 1996

Filed:

May 15, 1995

Appl. No.:

8/441571

Inventors:

Humberto F. Casal - Austin TX
Hehching H. Li - Austin TX
David M. Wu - Spring TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128
G06F 1100

US Classification:

39518508

Abstract:

The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ("PLL") circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.

US Patent:

56191588, Apr 8, 1997

Filed:

Aug 18, 1995

Appl. No.:

8/516704

Inventors:

Humberto F. Casal - Austin TX
Joel R. Davidson - Austin TX
Hehching H. Li - Austin TX
Yuan C. Lo - Austin TX
Trong D. Nguyen - Webster TX
Campbell H. Snyder - Austin TX
Nandor G. Thoma - Plano TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 513

US Classification:

327292

Abstract:

A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.

US Patent:

58225960, Oct 13, 1998

Filed:

Nov 6, 1995

Appl. No.:

8/554206

Inventors:

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX
Nandor Gyorgy Thoma - Plano TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 2100
G06F 1300

US Classification:

39575004

Abstract:

During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.

US Patent:

60237783, Feb 8, 2000

Filed:

Dec 12, 1997

Appl. No.:

8/989838

Inventors:

Hehching Harry Li - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714726

Abstract:

A method and an apparatus utilizing mux scan flip-flops to test for timing-related defects. In one embodiment, a delay circuit is used to act as a buffer for a scan enable signal received by the mux scan flip-flops of a test circuit. The scan mode signal is first sent to the delay circuit, which then distributes the scan mode signal to the mux scan flip-flops. Since each delay circuit can serve as the buffer for numerous mux scan flip-flops, the scan mode signal may be sent initially to a smaller number of delay circuits instead of the thousands of mux scan flip-flops that may be distributed throughout the entire integrated circuit. Furthermore, in one embodiment the delay circuit delays propagation of active-to-inactive transitions of the scan enable signal by one clock cycle, synchronizing the system clock cycle with the active-to-inactive transitions of the scan mode signal. In one embodiment, inactive-to-active transitions of the scan enable signal are propagated without the one clock cycle delay. With the present invention, the mux scan flip-flops may be loaded and unloaded with test data at slower scan clock speeds, and the integrated circuit may be operated at full system clock speeds for as few as two cycles to detect speed-related defects in accordance with the teachings of the present invention.