Henry T Chen

US Patent:

6580156, Jun 17, 2003

Filed:

Apr 4, 2002

Appl. No.:

10/115013

Inventors:

Akira Ito - Irvine CA
Henry Kuoshun Chen - Irvine CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 2358

US Classification:

257665, 257529, 257173, 257209, 438215

Abstract:

An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

US Patent:

6770948, Aug 3, 2004

Filed:

Apr 9, 2003

Appl. No.:

10/409584

Inventors:

Akira Ito - Irvine CA
Henry Kuoshun Chen - Irvine CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 2900

US Classification:

257529, 257173, 257209, 257665, 257910, 1022024, 3612751, 438467, 438600, 438601

Abstract:

An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

US Patent:

6950355, Sep 27, 2005

Filed:

Dec 18, 2001

Appl. No.:

10/020208

Inventors:

Surya Battacharya - Irvine CA, US
Ming Chen - Mission Viejo CA, US
Liming Tsau - Irvine CA, US
Henry Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

365201, 365154

Abstract:

A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e. g. , wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

US Patent:

7009832, Mar 7, 2006

Filed:

Mar 14, 2005

Appl. No.:

11/078511

Inventors:

Henry KuoShun Chen - Irvine CA, US
Akira Ito - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01G 4/228

US Classification:

3613061, 361309, 361329, 257306, 257310, 29 2541

Abstract:

A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a transverse arm, and a via. The upright arm has a top end and a bottom end that extend at substantially right angles to a central axis of the upright arm. The transverse arm has a left and right end that extend at substantially right angles to a central axis of the transverse arm. The upright arm and the transverse arm intersect to form a cross-like pattern and the top, bottom, left and right ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the upright and transverse arms.

US Patent:

7151660, Dec 19, 2006

Filed:

Jan 4, 2006

Appl. No.:

11/324221

Inventors:

Henry KuoShun Chen - Irvine CA, US
Akira Ito - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01G 4/228

US Classification:

3613061, 361309, 361329, 257306, 257310, 29 2541

Abstract:

A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second arm, and a via. The first arm has a first end and a second end. The second arm has a third end and a fourth end. The first arm and the second arm intersect and the first, second, third and fourth ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the first and second arms.

US Patent:

7161213, Jan 9, 2007

Filed:

Aug 5, 2004

Appl. No.:

10/911720

Inventors:

Akira Ito - Irvine CA, US
Henry K. Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 27/01
H01L 21/338

US Classification:

257349, 438173

Abstract:

A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.

US Patent:

7227238, Jun 5, 2007

Filed:

Jun 21, 2004

Appl. No.:

10/871569

Inventors:

Akira Ito - Irvine CA, US
Henry K. Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 29/00

US Classification:

257529, 257173, 257209, 257665, 257910, 1022024, 3612751, 438467, 438600, 438601

Abstract:

An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

US Patent:

7382024, Jun 3, 2008

Filed:

Jan 3, 2007

Appl. No.:

11/648651

Inventors:

Akira Ito - Irvine CA, US
Henry K Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 27/01
H01L 21/00
H01L 21/338

US Classification:

257349, 438156, 438173

Abstract:

A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.