Henry D Cook

US Patent:

20230029660, Feb 2, 2023

Filed:

Oct 6, 2022

Appl. No.:

17/961137

Inventors:

- San Mateo CA, US
Wesley Waylon Terpstra - San Mateo CA, US
Henry Cook - Berkeley CA, US

International Classification:

G06F 12/0804
G06F 12/128

Abstract:

Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

US Patent:

20230033550, Feb 2, 2023

Filed:

Oct 6, 2022

Appl. No.:

17/961146

Inventors:

- San Mateo CA, US
Wesley Waylon Terpstra - San Mateo CA, US
Henry Cook - Berkeley CA, US
Leigang Kou - Austin TX, US

International Classification:

H01S 5/042
G01N 29/24
H01S 5/06
H01S 5/10

Abstract:

Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

US Patent:

20210365609, Nov 25, 2021

Filed:

Jun 28, 2021

Appl. No.:

17/361238

Inventors:

- San Mateo CA, US
Richard Xia - San Francisco CA, US
Derek Pappas - Palo Alto CA, US
Mark Nugent - San Mateo CA, US
Henry Cook - Berkeley CA, US
Wesley Waylon Terpstra - San Mateo CA, US
Pin Hung Chen - Cupertino CA, US

International Classification:

G06F 30/20
G06F 30/30

Abstract:

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

US Patent:

20210286724, Sep 16, 2021

Filed:

May 27, 2021

Appl. No.:

17/332286

Inventors:

- San Mateo CA, US
Wesley Waylon Terpstra - San Mateo CA, US
Henry Cook - Berkeley CA, US

International Classification:

G06F 12/0804
G06F 12/128

Abstract:

Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

US Patent:

20200387659, Dec 10, 2020

Filed:

Apr 17, 2020

Appl. No.:

16/851966

Inventors:

- San Mateo CA, US
Henry Cook - Berkeley CA, US
Wesley Waylon Terpstra - San Mateo CA, US

International Classification:

G06F 30/398
G06F 30/333

Abstract:

Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

US Patent:

20200042664, Feb 6, 2020

Filed:

Aug 1, 2019

Appl. No.:

16/528911

Inventors:

- San Mateo CA, US
Richard Xia - San Francisco CA, US
Derek Pappas - Palo Alto CA, US
Mark Nugent - San Mateo CA, US
Henry Cook - Berkeley CA, US
Wesley Waylon Terpstra - San Mateo CA, US
Pin Hung Chen - Cupertino CA, US

International Classification:

G06F 17/50

Abstract:

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.