Henry E Edwards

US Patent:

6498502, Dec 24, 2002

Filed:

Dec 14, 2000

Appl. No.:

09/737365

Inventors:

Henry L. Edwards - Garland TX
Theodore S. Moise - Los Altos CA
Glen D. Wilk - New Providence NJ

Assignee:

Texas Instrument Incorporated - Dallas TX

International Classification:

G01R 31302

US Classification:

324750, 324765, 438 17

Abstract:

An apparatus and method for evaluating semiconductor structures and devices are provided. A method for evaluating at least one selected electrical property of a semiconductor device ( ) in relation to a selected geometric dimension of the semiconductor device ( ). The method further includes forming a plurality of semiconductor devices ( ) on a substrate ( ), the devices ( ) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices ( ) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device ( ). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.

US Patent:

6555476, Apr 29, 2003

Filed:

Dec 21, 1998

Appl. No.:

09/217123

Inventors:

Leif C. Olsen - Plano TX
Leland S. Swanson - McKinney TX
Henry L. Edwards - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

438692, 438695, 438697, 438700, 438706, 438723, 438724

Abstract:

Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively, silicon carbonitride or silicon carboxide can be used.

US Patent:

6561868, May 13, 2003

Filed:

Nov 30, 2000

Appl. No.:

09/727187

Inventors:

Henry Litzmann Edwards - Garland TX
Sung-Jen Fang - Richardson TX
Thomas M. Moore - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B24B 4900

US Classification:

451 8, 451 9, 451 41, 451288

Abstract:

A system for controlling a polishing machine during polishing of a workpiece, such as a semiconductor wafer, includes a carrier which has an interface surface for engaging a workpiece and establishing ultrasonic coupling thereto. At least one crystal oscillator is ultrasonically coupled to the carrier and operates at a resonant frequency in an ultrasonic band which is indicative of a desired polishing depth of the workpiece, such as the endpoint of polishing. A detector circuit provides an output signal which is representative of an output level of the crystal oscillator. A processor circuit receives the signal from the detector circuit and provides a signal to the polishing machine when the amplitude of the signal from the detector circuit indicates that the desired polishing endpoint has been reached. A number of crystal oscillators can be spatially arranged on the carrier to establish a local polishing depth detection array.

US Patent:

6867100, Mar 15, 2005

Filed:

Dec 19, 2002

Appl. No.:

10/326214

Inventors:

Henry L. Edwards - Garland TX, US
Sameer Pendharkar - Richardson TX, US
Joe Trogolo - Plano TX, US
Tathagata Chatterjee - Allen TX, US
Taylor Efland - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/336

US Classification:

438266, 438279, 438301

Abstract:

The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (), and an oxide region () overlapping the moat region. A double-diffusion region () is formed within the oxide region, having end cap regions () that are effectively deactivated utilizing geometric and implant manipulations.

US Patent:

7091556, Aug 15, 2006

Filed:

Dec 24, 2003

Appl. No.:

10/746978

Inventors:

Henry Litzmann Edwards - Garland TX, US
Sameer Pendharker - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/76
H01L 21/336

US Classification:

257336, 257339, 257344, 438197, 438306

Abstract:

The present invention provides, in one embodiment, a transistor (). The transistor () comprises a doped semiconductor substrate () and a drain-extended well () having a curved region () and a straight region () surrounded by the doped semiconductor substrate (). The drain-extended well () has an opposite dopant type as the doped semiconductor substrate (). The transistor () further includes a centered source/drain () surrounded by the drain-extended well () and separated from an outer perimeter () of the drain-extended well (). A separation in the curved region () is greater than a separation in the straight region (). Other embodiments of the present invention include an integrated circuit () and a method of manufacturing a transistor ().

US Patent:

7141455, Nov 28, 2006

Filed:

Nov 12, 2003

Appl. No.:

10/712455

Inventors:

Binghua Hu - Plano TX, US
Howard S. Lee - Plano TX, US
Henry L. Edwards - Garland TX, US
John Lin - Chelmsford MA, US
Vladimir N. Bolkhovsky - Framingham MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/332

US Classification:

438135, 438306, 438305

Abstract:

A double diffused region (), (), () is formed in an epitaxial layer (). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

US Patent:

7466009, Dec 16, 2008

Filed:

Jun 5, 2006

Appl. No.:

11/422221

Inventors:

Martin Mollat - McKinney TX, US
Tathagata Chatterjee - Allen TX, US
Henry L. Edwards - Garland TX, US
Lance S. Robertson - Rockwall TX, US
Richard B. Irwin - Richardson TX, US
Binghua Hu - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/93
H01L 23/62

US Classification:

257577, 257E21608, 257260, 257360

Abstract:

The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.

US Patent:

7595649, Sep 29, 2009

Filed:

Sep 25, 2007

Appl. No.:

11/860993

Inventors:

Tathagata Chatterjee - Allen TX, US
Joe R. Trogolo - Plano TX, US
Kaiyuan Chen - Dallas TX, US
Henry Litzmann Edwards - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/26

US Classification:

324719, 324769, 438 17

Abstract:

Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.