Henry Chuck Lee

US Patent:

6627534, Sep 30, 2003

Filed:

Feb 5, 2001

Appl. No.:

09/777354

Inventors:

Henry F. Lee - Milpitas CA 95035

International Classification:

H01L 21768

US Classification:

438624, 438637

Abstract:

Semiconductor fabrication process and structure in which an evaporative material is deposited in a space between two conductors, a layer of porous material is formed adjacent to the evaporative material, and the evaporative material is evaporated through the porous material to leave a closed empty space between the conductors. The empty space has a dielectric constant on the order of 1. 0, which minimizes capacitive coupling between the conductors.

US Patent:

57605947, Jun 2, 1998

Filed:

Sep 30, 1996

Appl. No.:

8/723021

Inventors:

Henry Lee - San Francisco CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G01R 1512

US Classification:

324663

Abstract:

A method for monitoring contamination in a semiconductor wafer uses a capacitance-frequency measurement on MOS structures to calculate an impurity concentration. The silicon substrate along with an oxide layer is first biased into the inversion region using a variable frequency waveform generator superimposed upon a DC voltage bias. Next, the capacitance of the wafer is measured as a function of the varying frequency in order to develop a capacitance versus frequency curve. From this frequency response, a bandwidth (BW) is measured at a particular normalized capacitance point. The impurity concentration N is then derived using the formula N=G. times. BW, where G is the correlation constant. With an a priori knowledge of impurity concentration, N, the constant G may be derived by measuring a bandwidth of the capacitance versus frequency curve. Once the constant G is determined, future evaluation of impurity concentration can be made by a capacitance measurement.

US Patent:

63099489, Oct 30, 2001

Filed:

Jan 11, 1999

Appl. No.:

9/229784

Inventors:

Xi-Wei Lin - Fremont CA
Henry Lee - San Francisco CA
Ian R. Harvey - Kaysville UT

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2176

US Classification:

438424

Abstract:

A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

US Patent:

58800069, Mar 9, 1999

Filed:

May 22, 1998

Appl. No.:

/083674

Inventors:

Xi-Wei Lin - Fremont CA
Henry Lee - San Francisco CA
Ian R. Harvey - Kaysville UT

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2184

US Classification:

438424

Abstract:

A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

US Patent:

58830111, Mar 16, 1999

Filed:

Jun 18, 1997

Appl. No.:

8/878451

Inventors:

Xi-Wei Lin - Fremont CA
Satyendra Sethi - Pleasanton CA
Henry Lee - San Francisco CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2100

US Classification:

438747

Abstract:

A method of removing an inorganic antireflective coating from a semiconductor substrate and a method of forming an integrated circuit (IC) are provided. In the former method, a sacrificial layer is formed over a semiconductor substrate, the layer being selectively removable from the substrate and compatible with photolithography. An inorganic antireflective coating such as SiON is then formed over the sacrificial layer. Thereafter, the sacrificial layer is removed from the substrate to lift the coating off the substrate. Preferred materials for the sacrificial layer include TiN, tetraethyl orthosilicate-based silicon oxide, spin-on-glass (SOG) such as hydrogen silsesquioxane and methyl silsesquioxane, and porous polymeric materials. In the latter method, a patterned layer of photoresist material is formed over the anitreflective coating. The portions of the antireflective coating, the sacrificial layer, and the semiconductor substrate which are not covered by the patterned layer of photoresist material are then removed to define features of an IC.

US Patent:

57535612, May 19, 1998

Filed:

Sep 30, 1996

Appl. No.:

8/723903

Inventors:

Henry C. Lee - San Francisco CA
Calvin T. Gabriel - Cupertino CA
Jie Zheng - Palo Alto CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2176

US Classification:

438424

Abstract:

Disclosed is a method for making a shallow trench structure in a semiconductor substrate. The method includes: (a) forming a mask over a semiconductor substrate, the mask being provided with an aperture extending therethrough which exposes a region of the semiconductor substrate, the aperture having substantially vertical sidewalls; (b) depositing a blanket of silicon over the mask and within the aperture; (c) anisotropically etching the deposited silicon to form temporary spacers having curved profiles at the sidewalls of the aperture, the temporary spacers transferring the curved profiles to a mouth of a shallow trench being etched at the region of the semiconductor substrate as the temporary spacers are etched away; (d) whereby a shallow trench structure is formed where the mouth has a curved profile.

US Patent:

20200354831, Nov 12, 2020

Filed:

May 7, 2019

Appl. No.:

16/405347

Inventors:

- Sunnyvale CA, US
Henry LEE - San Jose CA, US

International Classification:

C23C 16/44
B08B 3/08
B08B 3/12

Abstract:

Aspects of the present disclosure include methods, apparatuses, and computer readable media for transporting, via an automated crane, a component toward a first station within a cleaning system, placing, via the automated crane, the component into a first tank at the first station, wherein the first tank contains a solution that cleans the component by removing at least a portion of residual materials on the component, transporting, via the automated crane, the component toward a second station within a cleaning system, placing, via the automated crane, the component into a second tank at the second station, wherein the second tank contains a fluid that rinses the at least a portion of the residual materials removed by the solution, transporting, via the automated crane, the component toward a third station within a cleaning system, and placing, via the automated crane, the component into a chamber at the third station, wherein the chamber provides a gas or air that dries the fluid on the component.