Henry H Nguyen

US Patent:

6823402, Nov 23, 2004

Filed:

Nov 14, 2001

Appl. No.:

10/001152

Inventors:

Patrick J. Smith - Houston TX
Jay B. Reimer - Houston TX
Ramesh A. Iyer - San Jose CA
Henry D. Nguyen - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1328

US Classification:

710 22, 710 23, 710 26, 710 48, 710 49, 710 52, 710308, 710309

Abstract:

In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem.

US Patent:

7054958, May 30, 2006

Filed:

Nov 14, 2001

Appl. No.:

10/001153

Inventors:

Ramesh A. Iyer - San Jose CA, US
Henry D. Nguyen - Houston TX, US
Patrick J. Smith - Houston TX, US
Jay B. Reimer - Houston TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 13/28

US Classification:

710 22, 710 33, 710 48, 710 52, 710260, 709212

Abstract:

In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

US Patent:

7663939, Feb 16, 2010

Filed:

May 30, 2006

Appl. No.:

11/442818

Inventors:

Henry Nguyen - Fountain Valley CA, US
Ngoc Le - Irvine CA, US

Assignee:

Kingston Technology Corporation - Fountain Valley CA

International Classification:

G11C 7/00

US Classification:

36518911, 365222

Abstract:

A memory module is disclosed. The memory module comprises a voltage supply; a memory interface coupled to the voltage supply; a plurality of memory components; and a voltage stabilizer converter (VSC) coupled to the memory interface and to the plurality of memory components, the VSC for ensuring that the plurality of memory components operate at their optimum performance level. A voltage stabilizer memory module (VSMM) in accordance with the present invention includes a printed circuit board (PCB) that contains memory chips, discrete components, a voltage stabilizer converter, and other related components. The voltage stabilizer converter uses system voltage supply as its input and its output is the voltage supply for the DRAM components. Accordingly, the VSSM is more adaptable, more stable and has better performance than conventional memory modules.

US Patent:

8433706, Apr 30, 2013

Filed:

May 18, 2011

Appl. No.:

13/110764

Inventors:

Geoffrey Wade - Irvine CA, US
Mark Reyes - Irvine CA, US
Henry Nguyen - Irvine CA, US
Christopher Ploski - Irvine CA, US

Assignee:

Digital Map Products, Inc. - Irvine CA

International Classification:

G06F 7/00
G06F 17/30

US Classification:

707723, 707748, 707752

Abstract:

Systems and methods for customizing the display of a set of data using a preference stack interface. The preference stack interface allows a user to interact with an ordered list of criterion objects. Each criterion object corresponds to an attribute of the data set to be presented to the user. In response to a change in the order of the criterion objects in the preference stack, a rendering of the dataset can be updated to differently and visually emphasize items according to which criterion objects each item meets.

US Patent:

8602096, Dec 10, 2013

Filed:

Jun 28, 2011

Appl. No.:

13/170608

Inventors:

Peter Olenick - Spring TX, US
Henry Nguyen - Houston TX, US
Robert Hodge - Cypress TX, US
Ronnie Royer - Spring TX, US

Assignee:

Weatherford/Lamb, Inc. - Houston TX

International Classification:

E03B 3/18

US Classification:

166233, 166157, 166205

Abstract:

Operators manufacture a wellscreen by forming a wire-wrapped screen on a base pipe. Rather than stopping and restarting winding, the desired length of screen is completed along the base pipe, and then the wire screen is segmented into a plurality of screen sections as required for the various zones and details of the implementation. Operators arrange the screen sections relative to one another on the base pipe, which can have different lengths with and without perforations. On the free ends of these separate screen sections, mating split ring components fit around the free ends and the base pipes. Male edges of one split ring component mate to complementary female edges of another to form the end ring around the screen section and base pipe, and longitudinal welds made in seams along the mating edges affix the split ring components together.

US Patent:

20030093594, May 15, 2003

Filed:

Nov 14, 2001

Appl. No.:

10/000990

Inventors:

Patrick Smith - Houston TX, US
Jay Reimer - Houston TX, US
Ramesh Iyer - San Jose CA, US
Henry Nguyen - Houston TX, US

International Classification:

G06F003/00

US Classification:

710/048000

Abstract:

In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed.

US Patent:

20060259659, Nov 16, 2006

Filed:

May 12, 2006

Appl. No.:

11/383055

Inventors:

Roger Castille - Houston TX, US
Natarajan Seshan - Bellaire TX, US
Marco Lazar - Houston TX, US
Henry C. Nguyen - Houston TX, US

International Classification:

G06F 3/00

US Classification:

710036000

Abstract:

A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues data transfer requests. The transfer controller includes separate control of data source and data destination in a data transfer corresponding to the data transfer requests. The transfer controller includes a data transfer program register and active source and destination registers. The transfer controller operates from the active source and destination registers. Upon completion of a data transfer the transfer controller writes data transfer parameters from the data transfer program register to the active source and destination registers.

US Patent:

20060259660, Nov 16, 2006

Filed:

May 12, 2006

Appl. No.:

11/383063

Inventors:

Roger Castille - Houston TX, US
Natarajan Seshan - Bellaire TX, US
Henry C. Nguyen - Houston TX, US
Marco Lazar - Houston TX, US
Jason Jones - Richmond TX, US

International Classification:

G06F 3/00

US Classification:

710036000

Abstract:

A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.