Henry A Nye from 11 York St, Beacon, NY 12508, Phone: 2038047623

Resumes

Alliance Manager For Tcs Client

view source

Location:

Neenah, Wisconsin

Industry:

Computer Networking

Us Patents

Alpha Particle Shield For Integrated Circuit
view source
US Patent:

20020105059, Aug 8, 2002
Filed:

Feb 6, 2001
Appl. No.:

09/777540
Inventors:

Richard Wachnik - Mount Kisco NY, US
Henry Nye - Brookfield CT, US
Charles Davis - Fishkill NY, US
Theodore Zabel - Yorktown Heights NY, US
Phillips Restle - Katonah NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L021/44
H01L023/552
H01L023/48
H01L023/52
H01L029/40
US Classification:

257/660000, 257/758000, 257/768000, 257/765000, 257/750000
Abstract:

An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

Support Structures For Wirebond Regions Of Contact Pads Over Low Modulus Materials
view source
US Patent:

20040058520, Mar 25, 2004
Filed:

Sep 20, 2002
Appl. No.:

10/251453
Inventors:

Lloyd Burrell - Poughkeepsie NY, US
Douglas Kemerer - Essex Junction VT, US
Henry Nye - Brookfield CT, US
Hans-Joachim Barth - Muenchen, DE
Emmanuel Crabbe - Chappaqua NY, US
David Anderson - Gulf Shores AL, US
Joseph Chan - Fishkill NY, US
International Classification:

H01L021/44
US Classification:

438/612000
Abstract:

A semiconductor device () having support structures () beneath wirebond regions () of contact pads () and a method of forming same. Low modulus dielectric layers () are disposed over a workpiece (). Support structures () are formed in the low modulus dielectric layers (), and support vias () are formed between the support structures (). A high modulus dielectric film () is disposed between each low modulus dielectric layer (), and a high modulus dielectric layer () is disposed over the top low modulus dielectric layer (). Contact pads () are formed in the high modulus dielectric layer (). Each support via () within the low modulus dielectric layer () resides directly above a support via () in the underlying low modulus dielectric layer (), to form a plurality of via support stacks within the low modulus dielectric layers ().

Insulative Cap For Laser Fusing
view source
US Patent:

20040217384, Nov 4, 2004
Filed:

Jun 3, 2004
Appl. No.:

10/860470
Inventors:

Thomas McDevitt - Underhill VT, US
William Motsiff - Essex Junction VT, US
Henry Nye - Brookfield CT, US
International Classification:

H01L027/10
US Classification:

257/202000
Abstract:

A semiconductor device having at least one fuse and an alignment mark formed therein. An etch resistant layer over the surface of the fuse and alignment mark, which provides a uniform passivation thickness for use in conjunction with laser fuse deletion processes.

Immersion Plating And Plated Structures
view source
US Patent:

20040219384, Nov 4, 2004
Filed:

May 1, 2003
Appl. No.:

10/426725
Inventors:

Emanuel Cooper - Scarsdale NY, US
Charles Goldsmith - Poughkeepsie NY, US
Stephen Kilpatrick - Lagrangeville NY, US
Carmen Mojica - Dorado PR, US
Henry Nye - Brookfield CT, US
Assignee:

International Business Machines Corporation
International Classification:

B32B015/00
US Classification:

428/646000, 428/615000, 428/936000
Abstract:

A first metal is plated onto a substrate comprising a second metal by immersing the substrate into a bath comprising a compound of the first metal and an organic diluent. The second metal is more electropositive than the first metal. The organic diluent has a boiling point higher than a eutectic point in a phase diagram of the first and second metals. The bath is operated above the eutectic point but below the melting point of the second metal. For example, bismuth is immersion plated onto lead-free tin-based solder balls, and subsequently redistributed by fluxless reflow. Plated structures are also provided.

Inhibition Of Tin Oxide Formation In Lead Free Interconnect Formation
view source
US Patent:

20050026450, Feb 3, 2005
Filed:

Jul 30, 2003
Appl. No.:

10/604560
Inventors:

Emanuel Cooper - Scarsdale NY, US
John Cotte - New Fairfield CT, US
Lisa Fanti - Hopewell Junction NY, US
David Eichstadt - North Salem NY, US
Stephen Kilpatrick - Lagrangeville NY, US
Henry Nye - Brookfield CT, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

H01L021/44
H01L021/302
US Classification:

438745000, 438687000
Abstract:

A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.

Ball Limiting Metallurgy, Interconnection Structure Including The Same, And Method Of Forming An Interconnection Structure
view source
US Patent:

20050118437, Jun 2, 2005
Filed:

Dec 1, 2003
Appl. No.:

10/724938
Inventors:

Yu-Ting Cheng - HsinChu, TW
Stefanie Chiras - Peekskill NY, US
Donald Henderson - Ithaca NY, US
Sung-Kwon Kang - Chappaqua NY, US
Stephen Kilpatrick - Olney MD, US
Henry Nye - Brookfield CT, US
Carlos Sambucetti - Vallejo CA, US
Da-Yuan Shih - Poughkeepsie NY, US
International Classification:

C23C014/00
B32B015/08
US Classification:

428458000, 427524000, 427402000
Abstract:

A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

Interconnections For Flip-Chip Using Lead-Free Solders And Having Reaction Barrier Layers
view source
US Patent:

20050224966, Oct 13, 2005
Filed:

Mar 31, 2004
Appl. No.:

10/815103
Inventors:

Keith Fogel - Hopewell Junction NY, US
Balaram Ghosal - Fishkill NY, US
Sung Kang - Chappaqua NY, US
Stephen Kilpatrick - Olney MD, US
Paul Lauro - Brewster NY, US
Henry Nye - Brookfield CT, US
Da-Yuan Shih - Poughkeepsie NY, US
International Classification:

H01L023/48
US Classification:

257737000, 257778000
Abstract:

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Immersion Plating And Plated Structures
view source
US Patent:

20050238906, Oct 27, 2005
Filed:

Jun 28, 2005
Appl. No.:

11/167277
Inventors:

Emanuel Cooper - Scarsdale NY, US
Charles Goldsmith - Poughkeepsie NY, US
Stephen Kilpatrick - Lagrangeville NY, US
Carmen Mojica - Dorado PR, US
Henry Nye - Brookfield CT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B32B015/01
C25D003/60
US Classification:

428646000, 205253000
Abstract:

A first metal is plated onto a substrate comprising a second metal by immersing the substrate into a bath comprising a compound of the first metal and an organic diluent. The second metal is more electropositive than the first metal. The organic diluent has a boiling point higher than a eutectic point in a phase diagram of the first and second metals. The bath is operated above the eutectic point but below the melting point of the second metal. For example, bismuth is immersion plated onto lead-free tin-based solder balls, and subsequently redistributed by fluxless reflow. Plated structures are also provided.