Hetal N Gaywala

US Patent:

20130135017, May 30, 2013

Filed:

Nov 29, 2011

Appl. No.:

13/306828

Inventors:

Ian W. Jones - Palo Alto CA, US
Suwen Yang - Mountain View CA, US
Mark R. Greenstreet - Vancouver, CA
Hetal N. Gaywala - Mountain View CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

ORACLE INTERNATIONAL CORPORATION - Redwood City CA

International Classification:

H03L 7/06
H03L 7/00

US Classification:

327142, 327141, 327155, 327162

Abstract:

The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.