Hidenobu Matsumura - Santa Clara CA Hiroaki Yamoto - Santa Clara CA Koji Takahashi - Santa Clara CA
Assignee:
Advantest Corp. - Tokyo
International Classification:
G06F 1750
US Classification:
716 6, 714738
Abstract:
A semiconductor integrated circuit design and evaluation system for designing an LSI device under an electric design automation (EDA) environment and for evaluating a test pattern produced based on the CAD data derived in the design stage of the LSI device. The system includes an EDA environment for designing an LSI device and evaluating functions of the designed LSI device by a device logic simulator, a dump file for storing data expressed by an event base obtained by executing the device logic simulation, an LSI tester simulator for generating a test pattern and an expected value pattern in a cycle base, a cycle-event converter for converting the test pattern from the LSI tester simulator in the cycle base to a test pattern of the event base, a first memory for storing the event based test pattern from the cycle-event converter, a second memory for storing the data from the dump file, and a comparator for synchronizing the data stored in the first and second memories by comparing the timing relationship between the two and extracting output data of the device under test from the dump file corresponding to the test pattern from the LSI tester simulator.
James Alan Turnquist - Santa Clara CA Shigeru Sugamori - Santa Clara CA Rochit Rajsuman - Santa Clara CA Hiroaki Yamoto - Santa Clara CA
Assignee:
Advantest Corp. - Tokyo
International Classification:
G01R 3128
US Classification:
714738
Abstract:
An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.
Application Specific Event Based Semiconductor Memory Test System
Shigeru Sugamori - Santa Clara CA Koji Takahashi - Santa Clara CA Hiroaki Yamoto - Santa Clara CA
Assignee:
Advantest Corp. - Tokyo
International Classification:
G01M 1900
US Classification:
702122, 365201
Abstract:
A semiconductor test system for testing semiconductor devices has a plurality of different tester modules and an algorithmic pattern generator (ALPG) for generating an algorithmic pattern specific to an intended memory, thereby achieving a low cost and application specific memory test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, an ALPG module for generating an algorithmic pattern which is specific to the memory, a test system main frame to accommodate a combination of the tester modules and the ALPG module, a test fixture for electrically connecting the tester modules and a device under test, a performance board provided on the test fixture for mounting the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.
Modular Architecture For Memory Testing On Event Based Test System
Rochit Rajsuman - Santa Clara CA Shigeru Sugamori - Santa Clara CA Hiroaki Yamoto - Santa Clara CA
Assignee:
Advantest Corp. - Tokyo
International Classification:
G01R 3128
US Classification:
714738
Abstract:
An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.
James Alan Turnquist - Santa Clara CA Shigeru Sugamori - Santa Clara CA Hiroaki Yamoto - Santa Clara CA
Assignee:
Advantest Corp. - Tokyo
International Classification:
G06F 1100
US Classification:
703 14, 703 17, 703 27, 714738, 714742
Abstract:
A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.
A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].
High Speed Semiconductor Test System Using Radially Arranged Pin Cards
Rochit Rajsuman - Santa Clara CA Hiroaki Yamoto - Santa Clara CA
Assignee:
Advantest Corp. - Tokyo
International Classification:
G01R 3102
US Classification:
3241581, 324765
Abstract:
A high speed semiconductor test system is so designed that pin cards in a test head are arranged in radial directions where the DUT is placed over the center of the test head. Since each of the pin cards is arranged radially, the side which faces the center is close to the DUT, and time critical components in the pin card are formed in an area close to the side of that faces the center, thereby minimizing the round-trip-delay (RTD). Moreover, each pin card is distanced equally from the DUT. Thus, the variation in the length of path connecting between the pin card and the DUT is minimized, and accordingly, the variation in RTD is also minimized.
Rochit Rajsuman - Santa Clara CA, US Hiroaki Yamoto - Santa Clara CA, US
Assignee:
Advantest Corp. - Tokyo
International Classification:
G01R031/28
US Classification:
714724
Abstract:
A method of evaluating a core based SoC detects and localizes faults in the cores or interconnects between the cores with high accuracy and observability. The method includes the steps of building two or more metal layers to create core I/O pads having all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, testing the SoC as a whole by applying test vectors to the SoC through chip I/O pads and evaluating response outputs of the SoC, testing each core in the SoC by applying core specific test vectors to the core through the core I/O pads on the top metal layer of the core and evaluating response outputs of the core, and finding a location of a fault when the fault is detected when testing the SoC chip as a whole or when testing each of the cores.