Hisashige Ando

US Patent:

49690299, Nov 6, 1990

Filed:

Apr 27, 1987

Appl. No.:

7/047551

Inventors:

Hisashige Ando - Santa Clara CA
Hung C. Lai - Cupertino CA
John J. Zasio - Sunnyvale CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H01L 2710
H01L 2702

US Classification:

357 45

Abstract:

Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurlity of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells.

US Patent:

41504410, Apr 17, 1979

Filed:

Mar 20, 1978

Appl. No.:

5/890627

Inventors:

Hisashige Ando - Santa Clara CA

Assignee:

Microtechnology Corporation - Sunnyvale CA

International Classification:

G11C 1140

US Classification:

365189

Abstract:

A clocked static memory comprising a memory matrix, sense driver and a logic circuit connected between a pair of data lines in the memory matrix. The memory matrix includes a plurality of static memory cells arranged in rows and columns and are of the type adapted to provide a voltage differential at the bit lines whenever that particular memory cell is selected. A logic circuit detects the actual data output on the bit lines and is buffered by an amplifier to provide a memory status output signal indicating the existence of valid data output.

US Patent:

50953567, Mar 10, 1992

Filed:

Oct 9, 1990

Appl. No.:

7/594309

Inventors:

Hisashige Ando - Santa Clara CA
Hung C. Lai - Cupertino CA
John J. Zasio - Sunnyvale CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H01L 2710
H01L 2702

US Classification:

357 45

Abstract:

Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurality of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells.

US Patent:

41625404, Jul 24, 1979

Filed:

Mar 20, 1978

Appl. No.:

5/887954

Inventors:

Hisashige Ando - Santa Clara CA

Assignee:

Fujitsu Limited

International Classification:

G11C 700
G11C 706

US Classification:

365194

Abstract:

A clocked memory comprising a memory matrix having a plurality of memory cells arranged in rows and columns on a semiconductor substrate; a plurality of word select lines in said memory matrix, a plurality of bit lines crossing said select lines and connecting to said memory cells in each column; a drive circuit for driving said word select lines; a plurality of presence amplifiers connected to said bit lines; and a sense clock line parallel to said word select lines and connected to a gate of a transistor in said presence amplifier; and a presense drive circuit connected to said sense clock line and operated by a clock signal, said presense drive circuit having a transistor with controlled charging capability so as to conduct said transistor responsive to the charge of the memory cell in said each column.