2801 Atlantic Ave, Long Beach, CA 90806 9494171812 (Phone)
California Anesthesia Assocs 3991 Macarthur Blvd Suite 200, Newport Beach, CA 92660 9494171812 (Phone)
Pain and Rehabilitation Consltnts Medical Grp 6699 Telegraph Ave Suite 202, Oakland, CA 94609 5106475101 (Phone)
Certifications:
Anesthesiology, 2004
Awards:
Healthgrades Honor Roll
Languages:
English
Hospitals:
2801 Atlantic Ave, Long Beach, CA 90806
California Anesthesia Assocs 3991 Macarthur Blvd Suite 200, Newport Beach, CA 92660
Pain and Rehabilitation Consltnts Medical Grp 6699 Telegraph Ave Suite 202, Oakland, CA 94609
Long Beach Memorial Medical Center 2801 Atlantic Avenue, Long Beach, CA 90806
Education:
Medical School Meharry Medical College School Of Medicine Graduated: 1998 Medical School Loma Linda University Med Center Graduated: 1998 Medical School San Joaquin Gen Hospital Graduated: 1998
Woodland Clinic Medical GrpWoodland Clinic 1321 Cottonwood St, Woodland, CA 95695 5306661631 (phone), 5306684839 (fax)
Education:
Medical School Harvard Medical School Graduated: 1993
Procedures:
Carpal Tunnel Decompression Arthrocentesis Lower Arm/Elbow/Wrist Fractures and Dislocations Shoulder Arthroscopy Shoulder Surgery
Conditions:
Fractures, Dislocations, Derangement, and Sprains Internal Derangement of Knee Intervertebral Disc Degeneration Lateral Epicondylitis Osteoarthritis
Languages:
English French Spanish Vietnamese
Description:
Dr. Tran graduated from the Harvard Medical School in 1993. He works in Woodland, CA and specializes in Orthopaedic Surgery. Dr. Tran is affiliated with Woodland Memorial Hospital.
A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.
Multipurpose And Programmable Pad Ring For An Integrated Circuit
Hoang T Tran - San Diego CA, US Howard A Baumer - Laguna Hills CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 3/00 G06F 13/00
US Classification:
710 11, 710 71, 710305
Abstract:
A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.
Method And Apparatus For Regulating Transceiver Power Consumption For A Transceiver In A Communications Network
Hoang Tan Tran - San Diego CA, US Mark Berman - Newport Coast CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 1/32
US Classification:
713324, 713300, 713320, 713323
Abstract:
A method and apparatus for regulating transceiver power consumption for a transceiver in a communications network. Data received by the transceiver is monitored to detect the presence or absence of a received data signal. A transceiver state machine is controlled to regulate transceiver power consumption in response to the presence of absence of the data received.
Multipurpose And Programmable Pad For An Integrated Circuit
Hoang T. Tran - Rancho Santa Fe CA, US Howard A. Baumer - Laguna Hills CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 3/00 G06F 13/00
US Classification:
710 8, 710 62, 710 63
Abstract:
A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.
Programmable Management Io Pads For An Integrated Circuit
Hoang T. Tran - Rancho Santa Fe CA, US Howard A. Baumer - Laguna Hills CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 3/00
US Classification:
710 12, 710 8, 710 10, 326 62
Abstract:
A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.
Method And Apparatus For Regulating Transceiver Power Consumption For A Transceiver In A Communications Network
Hoang Tan Tran - San Diego CA, US Mark Berman - Newport Coast CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 1/32
US Classification:
713324, 713300, 713320, 713323
Abstract:
A method and apparatus for regulating transceiver power consumption for a transceiver in a communications network. Data received by the transceiver is monitored to detect the presence or absence of a received data signal. A transceiver state machine is controlled to regulate transceiver power consumption in response to the presence of absence of the data received.
Multi-Port, Gigabit Serdes Transceiver Capable Of Automatic Fail Switchover
A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the transceiver can connect any of the serial ports to another serial port or to a parallel port. The transceiver further includes a switch, a logic core, and a bus. The switch is selectively coupled to at least a first port and a second port. The switch activates the first port and deactivates the second port based on satisfaction of a condition associated with the first port. The logic core operates the serial and parallel ports, and the bus connects the ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the ports. The ring structure provides efficient communication between the logic core and the ports.
Programmable Management Io Pads For An Integrated Circuit
Dec 2011 to 2000 Stakeholder Project CoordinatorUnitedHealth Group, OptumRx Irvine, CA Oct 2010 to Dec 2011 Project CoordinatorThe Tu Firm, APLC Fountain Valley, CA Apr 2010 to Oct 2010 Administrative/Personal AssistantCalifornia State University Fullerton, CA Jan 2009 to Jun 2010 Business Consultant
Education:
California State University Dec 2010 Bachelor of Arts in Business Administration
Ruhnau Riverside, CA 2005 to 2010 Clarke AssociateThe Toro Company Riverside, CA 2000 to 2003 New Products AssemblerThe Toro Company Riverside, CA 1995 to 2000 Final Test technicianThe Toro Company Riverside, CA 1991 to 1995 General AssemblerThe Toro Company Riverside, CA 1986 to 1991 Printed Circuit Board Assembler
Education:
MTI College Santa Ana, CA 2004 Associate in AutoCAD Drafting
Nov 2011 to 2000 Radiation TherapistOrange County Cyberknife and Radiation Oncology Center Fountain Valley, CA Mar 2013 to May 2013 Radiation Therapist
Education:
California State University, Long Beach Long Beach, CA 2006 to 2011 Bachelor of Science in Health Science with Radiation Therapy option
Carleton School Vancouver Saudi Arabia 1992-2000, Wellington Junior High School Edmonton Azores 2000-2002, M.E. Lazerte High School Edmonton Azores 2000-2004
Community:
Mark Wakefield, Bonny Harris, Joyce Reeves, Deeann Covey