Hong X Du

US Patent:

7115517, Oct 3, 2006

Filed:

Sep 29, 2003

Appl. No.:

10/674700

Inventors:

Yan Ye - Saratoga CA, US
Xiaoye Zhao - Mountain View CA, US
Hong Du - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/302
H01L 21/3065

US Classification:

438700, 438706, 438725, 252 791, 216 41

Abstract:

A method of fabricating an interconnect structure (e. g. , dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e. g. , copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e. g.

US Patent:

7413990, Aug 19, 2008

Filed:

Jun 12, 2006

Appl. No.:

11/423613

Inventors:

Yan Ye - Saratoga CA, US
Xiaoye Zhao - Mountain View CA, US
Hong Du - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/311

US Classification:

438700, 438706, 438725, 252 791, 216 37, 216 41

Abstract:

A method of fabricating an interconnect structure (e. g. , dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e. g. , copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e. g.

US Patent:

7962863, Jun 14, 2011

Filed:

May 6, 2008

Appl. No.:

12/115830

Inventors:

Bo Su - San Jose CA, US
Gaurav Verma - Sunnyvale CA, US
Hong Du - Saratoga CA, US
Rui-fang Shi - Cupertino CA, US
Scott Andrews - Mountain View CA, US

Assignee:

KLA-Tencor Corp. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 50, 716 51

Abstract:

Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer are provided. One method includes generating simulated images of the reticle features printed on the wafer using different generated models for a set of different values of exposure conditions. The method also includes determining one or more characteristics of the reticle features of the simulated images. In addition, the method includes comparing the one or more characteristics of the reticle features of the simulated images to one or more characteristics of the reticle features printed on the wafer using a lithography process. The method further includes selecting one of the different generated models as the model to be used for predicting the printability of the reticle features based on results of the comparing step.

US Patent:

8192900, Jun 5, 2012

Filed:

Feb 26, 2010

Appl. No.:

12/714159

Inventors:

Hong Du - Saratoga CA, US
Douglas J. Werner - Fremont CA, US
Yi Zheng - San Ramon CA, US

Assignee:

Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam

International Classification:

G03F 1/00

US Classification:

430 5

Abstract:

A method for patterning a wafer using a phase shifting photolithography that can produce a critical symmetrical 2-dimensional structure such as a magnetic write pole of a magnetic write head. In one aspect of the invention, a photolithographic mask has an opaque portion with narrow, transparent phase shifting regions at either side of the opaque portion. A non-phase shifted region extends beyond the narrow phase shifted portion at either side of the structure. The phase shifted regions are symmetrical about the opaque region so that the image produced on the wafer is completely symmetrical. In another aspect of the invention, a phase shifted region in formed in a transparent medium with non-phase shifted regions at either side of the phase shifted region. The transition between the phase shifted region and non-phase shifted region alone defines a pattern on the wafer, without the need for an opaque structure on the mask.

US Patent:

20040018742, Jan 29, 2004

Filed:

Mar 4, 2003

Appl. No.:

10/379980

Inventors:

Jim He - Sunnyvale CA, US
Meihua Shen - Fremont CA, US
Hong Du - Cupertino CA, US
Scott Williams - Sunnyvale CA, US

Assignee:

Applied Materials, Inc.

International Classification:

H01L021/302
H01L021/461

US Classification:

438/710000

Abstract:

The present invention includes a method for patterning a bilayer resist having a patterned upper resist layer over a lower resist layer formed on a substrate. In one embodiment of the present invention, the method includes an optional upper resist layer trimming step, an upper resist layer treatment step, and a lower resist layer etching step. In the upper resist layer trimming step, the upper resist layer is trimmed in a plasma of a first process gas. In the upper resist layer treatment step, the upper resist layer is treated in a plasma of a second process gas to increase its etch resistance during the subsequent lower resist layer etching step. In the lower resist etching step, the lower resist layer is etched in a plasma of a third process gas, using the upper resist layer as a mask.