Hong Ai-Yun Z Lin

Address:

22452 76 Ave, Oakland Gardens, NY 11364

Phone:

7182177516

VIN:

WBXPC93417WF15241

Make:

BMW

Model:

X3

Year:

2007

US Patent:

7560758, Jul 14, 2009

Filed:

Jun 29, 2006

Appl. No.:

11/427491

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/80

US Classification:

257288, 257382, 257E29143, 257622, 257902

Abstract:

The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

US Patent:

7816261, Oct 19, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/928356

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438664, 438682, 257E2177

Abstract:

The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

US Patent:

7977712, Jul 12, 2011

Filed:

Mar 31, 2008

Appl. No.:

12/059059

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Mount Kisco NY, US
Katherine L. Saenger - Ossining NY, US
Kai Xiu - Pleasantville NY, US
Haizhou Yin - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/04

US Classification:

257255, 257E29004

Abstract:

A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i. e. , typically the pFET) has asymmetric source and drain regions.

US Patent:

20030176368, Sep 18, 2003

Filed:

Sep 6, 2002

Appl. No.:

10/236135

Inventors:

Samuel Danishefsky - Englewood NJ, US
Kaustav Biswas - Thouand Oaks NY, US
Mark Chappell - Noblesville IN, US
Hong Lin - New York NY, US
Jon Njardarson - New York NY, US
Chul Lee - Princeton NJ, US
Alexy Rivkin - New York NY, US
Ting-Chao Chou - Paramus NJ, US

International Classification:

C07H017/08
C 07D 4 9/02
A61K031/7048
A61K031/427
A61K031/38
A61K031/365
C07D417/02

US Classification:

514/028000, 514/365000, 514/183000, 514/431000, 514/450000, 536/007400, 548/203000, 540/451000, 549/009000, 549/266000

Abstract:

The present invention provides compounds of formula (I): as described generally and in classes and subclasses herein. The present invention additionally provides pharmaceutical compositions comprising compounds of formula (I) and provides methods of treating cancer comprising administering a compound of formula (I).

US Patent:

20070221959, Sep 27, 2007

Filed:

Mar 22, 2006

Appl. No.:

11/308410

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/76

US Classification:

257213000

Abstract:

A raised source/drain field effect transistor has a surface of a raised source/drain that tapers downward in a direction of a gate electrode that is also included within the field effect transistor. The downward tapered surface is preferably an end surface. Due to the downward taper, the field effect transistor has a reduced gate to raised source/drain region capacitance. The downward taper also facilitates forming a halo region within the field effect transistor. Due to the raised source/drain, a silicide layer may be included within the raised source/drain region absent silicide penetration through a thin junction within an intrinsic source/drain region also included within the raised source/drain region.