Hong Yunyu C Lin

US Patent:

6743669, Jun 1, 2004

Filed:

Jun 5, 2002

Appl. No.:

10/164227

Inventors:

Hong Lin - Vancouver WA
Shiqun Gu - Vancouver WA
Peter McGrath - Portland OR

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218234

US Classification:

438238, 438210, 438382

Abstract:

A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si N is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.

US Patent:

6746925, Jun 8, 2004

Filed:

Mar 25, 2003

Appl. No.:

10/397451

Inventors:

Hong Lin - Vancouver WA
Shiqun Gu - Vancouver WA
Wai Lo - Lake Oswego OR
Jim Elmer - Vancouver WA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21336

US Classification:

438287, 438303, 438595, 438225, 438230, 438504, 438452

Abstract:

In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O plasma oxidation. The presence of the sidewall oxides minimizes encroachment under the gate edge.

US Patent:

6794304, Sep 21, 2004

Filed:

Jul 31, 2003

Appl. No.:

10/631528

Inventors:

Shiqun Gu - Vancouver WA
Masaichi Eda - Gresham OR
Peter McGrath - Portland OR
Hong Lin - Vancouver WA
Jim Elmer - Vancouver WA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

438740, 438742, 438754

Abstract:

A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

US Patent:

6806038, Oct 19, 2004

Filed:

Jul 8, 2002

Appl. No.:

10/190954

Inventors:

Shiqun Gu - Vancouver WA
Hong Lin - Vancouver WA
Ryan Tadashi Fujimoto - Gresham OR

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G03F 700

US Classification:

430318, 430323, 430322, 430329, 430330, 216 58, 216 63, 216 67, 216 69

Abstract:

A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrained chlorine gas. The substrate is heated on a chuck in a reaction chamber. A remote plasma is generated from ammonia gas and oxygen gas. The substrate is contacted with the ammonia and oxygen plasma, thereby withdrawing a substantial portion of the entrained chlorine gas from the polymer layer. A radio frequency potential is applied to the chuck on which the substrate resides, thereby creating a reactive ion etchant from the ammonia and oxygen plasma in the reaction chamber and removing the polymer layer from the top surface of the photoresist mask. The photoresist mask is thus exposed, and then removed in an ashing process.

US Patent:

6818516, Nov 16, 2004

Filed:

Jul 29, 2003

Appl. No.:

10/629496

Inventors:

Wai Lo - Lake Oswego OR
Hong Lin - Vancouver WA
Shiqun Gu - Vancouver WA
James R. B. Elmer - Vancouver WA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21336

US Classification:

438287, 438307

Abstract:

A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.

US Patent:

6864152, Mar 8, 2005

Filed:

May 20, 2003

Appl. No.:

10/442533

Inventors:

Venkatesh P. Gopinath - Fremont CA, US
Hong Lin - Vancouver WA, US
Verne Hornback - Camas WA, US
Dodd Defibaugh - Camas WA, US
Ynhi Le - Gresham OR, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L021/76

US Classification:

438427, 438700, 438703, 438424, 438749, 438750, 438751

Abstract:

Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

US Patent:

7081406, Jul 25, 2006

Filed:

Aug 10, 2004

Appl. No.:

10/915719

Inventors:

Wai Lo - Lake Oswego OR, US
Hong Lin - Vancouver WA, US
Shiqun Gu - Vancouver WA, US
Wilbur G. Catabay - Saratoga CA, US
Zhihai Wang - Sunnyvale CA, US
Wei-Jen Hsia - Saratoga CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21/4763

US Classification:

438620, 438614, 438669

Abstract:

An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

US Patent:

7189628, Mar 13, 2007

Filed:

Aug 31, 2004

Appl. No.:

10/931605

Inventors:

Venkatesh P. Gopinath - Fremont CA, US
Hong Lin - Vancouver WA, US
Verne Hornback - Camas WA, US
Dodd Defibaugh - Camas WA, US
Ynhi Le - Gresham OR, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21/461

US Classification:

438424, 438427, 438444, 438700, 438703, 438734, 438749, 438750, 438751, 438756, 438757, 438FOR 232, 257E21579

Abstract:

Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.