Hong Mei Lin

Address:

22452 76 Ave, Oakland Gardens, NY 11364

Phone:

7182177516

VIN:

WBXPC93417WF15241

Make:

BMW

Model:

X3

Year:

2007

US Patent:

7560758, Jul 14, 2009

Filed:

Jun 29, 2006

Appl. No.:

11/427491

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/80

US Classification:

257288, 257382, 257E29143, 257622, 257902

Abstract:

The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

US Patent:

7816261, Oct 19, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/928356

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438664, 438682, 257E2177

Abstract:

The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

US Patent:

7977712, Jul 12, 2011

Filed:

Mar 31, 2008

Appl. No.:

12/059059

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Mount Kisco NY, US
Katherine L. Saenger - Ossining NY, US
Kai Xiu - Pleasantville NY, US
Haizhou Yin - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/04

US Classification:

257255, 257E29004

Abstract:

A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i. e. , typically the pFET) has asymmetric source and drain regions.

US Patent:

8285414, Oct 9, 2012

Filed:

Mar 31, 2009

Appl. No.:

12/415348

Inventors:

Ehud Aharoni - Kfar Saba, IL
Robert J. Baseman - Brewster NY, US
Ramona Kei - Hopewell Junction NY, US
Oded Margalit - Ramat Gan, IL
Kevin Mackey - Wappingers Falls NY, US
Michal Rosen-Zvi - Jerusalem, IL
Raminderpal Singh - Cortlandt Manor NY, US
Noam Slonim - Jerusalem, IL
Hong Lin - Yorktown Heights NY, US
Fateh A. Tipu - Wappingers Falls NY, US
Adam D. Ticknor - Poughkeepsie NY, US
Timothy M. McCormack - Pleasant Valley NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 19/00

US Classification:

700175, 409232

Abstract:

A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.

US Patent:

8594826, Nov 26, 2013

Filed:

Sep 10, 2012

Appl. No.:

13/608032

Inventors:

Ehud Aharoni - Kfar Saba, IL
Robert J. Baseman - Brewster NY, US
Ramona Kei - Hopewell Junction NY, US
Oded Margalit - Ramat Gan, IL
Kevin Mackey - Wappingers Falls NY, US
Michal Rosen-Zvi - Jerusalem, IL
Raminderpal Singh - Essex Junction VT, US
Noam Slonim - Jerusalem, IL
Hong Lin - Yorktown Heights NY, US
Fateh A. Tipu - Wappingers Fall NY, US
Adam D. Ticknor - Poughkeepsie NY, US
Timothy M. McCormack - Pleasant Valley NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 19/00

US Classification:

700121, 438 16, 700108

Abstract:

A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.

US Patent:

20030176368, Sep 18, 2003

Filed:

Sep 6, 2002

Appl. No.:

10/236135

Inventors:

Samuel Danishefsky - Englewood NJ, US
Kaustav Biswas - Thouand Oaks NY, US
Mark Chappell - Noblesville IN, US
Hong Lin - New York NY, US
Jon Njardarson - New York NY, US
Chul Lee - Princeton NJ, US
Alexy Rivkin - New York NY, US
Ting-Chao Chou - Paramus NJ, US

International Classification:

C07H017/08
C 07D 4 9/02
A61K031/7048
A61K031/427
A61K031/38
A61K031/365
C07D417/02

US Classification:

514/028000, 514/365000, 514/183000, 514/431000, 514/450000, 536/007400, 548/203000, 540/451000, 549/009000, 549/266000

Abstract:

The present invention provides compounds of formula (I): as described generally and in classes and subclasses herein. The present invention additionally provides pharmaceutical compositions comprising compounds of formula (I) and provides methods of treating cancer comprising administering a compound of formula (I).

US Patent:

20070221959, Sep 27, 2007

Filed:

Mar 22, 2006

Appl. No.:

11/308410

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Hong Lin - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/76

US Classification:

257213000

Abstract:

A raised source/drain field effect transistor has a surface of a raised source/drain that tapers downward in a direction of a gate electrode that is also included within the field effect transistor. The downward tapered surface is preferably an end surface. Due to the downward taper, the field effect transistor has a reduced gate to raised source/drain region capacitance. The downward taper also facilitates forming a halo region within the field effect transistor. Due to the raised source/drain, a silicide layer may be included within the raised source/drain region absent silicide penetration through a thin junction within an intrinsic source/drain region also included within the raised source/drain region.