Hong Shen

US Patent:

7923842, Apr 12, 2011

Filed:

Mar 16, 2006

Appl. No.:

11/377690

Inventors:

Hong Shen - Camarillo CA, US
Ravi Ramanathan - Thousand Oaks CA, US
Qiuliang Luo - Moorpark CA, US
Robert W Warren - Newport Beach CA, US
Usama K Abdali - Aliso Viejo CA, US

Assignee:

Skyworks Solutions, Inc. - Woburn MA

International Classification:

H01L 23/48

US Classification:

257774, 257E23011, 257E23067

Abstract:

A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAS devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.

US Patent:

8415805, Apr 9, 2013

Filed:

Dec 17, 2010

Appl. No.:

12/971465

Inventors:

Hong Shen - Camarillo CA, US

Assignee:

Skyworks Solutions, Inc. - Woburn MA

International Classification:

H01L 23/48

US Classification:

257774, 257E21023, 257E21231, 438717

Abstract:

Etched wafers and methods of forming the same are disclosed. In one embodiment, a method of etching a wafer is provided. The method includes forming a metal hard mask on the wafer using electroless plating, patterning the metal hard mask, and etching a plurality of features on the wafer using an etcher. The plurality of featured are defined by the metal hard mask.

US Patent:

20110186966, Aug 4, 2011

Filed:

Apr 11, 2011

Appl. No.:

13/084467

Inventors:

Hong Shen - Camarillo CA, US
Ravi Ramanathan - Thousand Oaks CA, US
Qiuliang Luo - Moorpark CA, US
Robert W. Warren - Newport Beach CA, US
Usama K. Abdali - Aliso Viejo CA, US

Assignee:

SKYWORKS SOLUTIONS, INC. - Woburn MA

International Classification:

H01L 29/20
H01L 21/283

US Classification:

257615, 438653, 257E29089, 257E21159

Abstract:

A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAs devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.

US Patent:

20120153477, Jun 21, 2012

Filed:

Dec 17, 2010

Appl. No.:

12/972119

Inventors:

Hong Shen - Westlake Village CA, US

Assignee:

SKYWORKS SOLUTIONS, INC. - Woburn MA

International Classification:

H01L 23/532
H01L 21/768

US Classification:

257751, 438606, 257E21584, 257E23155

Abstract:

Methods for plating metal over features of a semiconductor wafer and devices that can be formed by these methods are disclosed. One such method includes forming a barrier layer over the substrate using electroless plating and forming a copper layer over the barrier layer. In some implementations, the semiconductor wafer is a GaAs wafer. Alternatively or additionally, the feature over which metal is plated can be a through-wafer via. In some implementations, a seed layer over the barrier layer can be formed using electroless plating.

US Patent:

20130193573, Aug 1, 2013

Filed:

Jan 27, 2012

Appl. No.:

13/360489

Inventors:

Hong Shen - Oak Park CA, US

Assignee:

SKYWORKS SOLUTIONS, INC. - Woburn MA

International Classification:

H01L 23/48
H01L 21/28
H01L 21/66

US Classification:

257741, 438 14, 438597, 438686, 257E21521, 257E2301, 257E21158

Abstract:

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

US Patent:

20130193575, Aug 1, 2013

Filed:

Jan 27, 2012

Appl. No.:

13/360431

Inventors:

Hong Shen - Oak Park CA, US

Assignee:

SKYWORKS SOLUTIONS, INC. - Woburn MA

International Classification:

H01L 23/48
H01L 21/768
H01L 21/02

US Classification:

257751, 438758, 257741, 438667, 257E21002, 257E2301, 257E21586, 257E23011

Abstract:

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To improve the copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

US Patent:

20130249095, Sep 26, 2013

Filed:

Mar 26, 2012

Appl. No.:

13/429725

Inventors:

Hong Shen - Oak Park CA, US

Assignee:

SKYWORKS SOLUTIONS, INC. - Woburn MA

International Classification:

H01L 23/48
H01L 21/50

US Classification:

257751, 438121, 257E2301, 257E21499

Abstract:

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

US Patent:

20130299985, Nov 14, 2013

Filed:

May 8, 2012

Appl. No.:

13/466792

Inventors:

Hong Shen - Oak Park CA, US

Assignee:

SKYWORKS SOLUTIONS, INC. - Woburn MA

International Classification:

H01L 23/532
H01L 21/283

US Classification:

257741, 438687, 257E23155, 257E21159

Abstract:

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.