Hong J Shen

US Patent:

6861418, Mar 1, 2005

Filed:

Dec 16, 2003

Appl. No.:

10/736243

Inventors:

Jingrong Cui - Foster City CA, US
Ruofei Zhang - Foster City CA, US
Hong Shen - San Francisco CA, US
Ji Yu Chu - Fremont CA, US
Fang-Jie Zhang - San Jose CA, US
Marcel Koenig - Burlingame CA, US
Steven Huy Do - San Jose CA, US
Xiaoyuan Li - Los Altos CA, US
Chung Chen Wei - Foster City CA, US
Peng Cho Tang - Moraga CA, US

Assignee:

Sugen, Inc. - South San Francisco CA

International Classification:

A61K031/33
A61K031/4738
C07D209/04
C07D209/34
C07D311/94

US Classification:

514183, 514408, 514415, 514456, 514319, 514322, 514327, 546199, 546201, 548452, 548465, 548469, 548486, 549396

Abstract:

The present invention relates to 4-arylindolinones, as well as pharmaceutical compositions thereof, capable of modulating protein kinase signal transduction in order to regulate, modulate and/or inhibit abnormal cell proliferation. The present invention also relates to methods for treating protein kinase related disorders.

US Patent:

20030069297, Apr 10, 2003

Filed:

Dec 20, 2001

Appl. No.:

10/023488

Inventors:

Jingrong Cui - Foster City CA, US
Ruofei Zhang - Foster City CA, US
Hong Shen - San Francisco CA, US
Ji Yu Chu - Fremont CA, US
Fang-Jie Zhang - San Jose CA, US
Marcel Koenig - Burlingame CA, US
Steven Do - San Jose CA, US
Xiaoyuan Li - Los Altos CA, US
Chung Wei - Foster City CA, US
Peng Tang - Moraga CA, US

Assignee:

Sugen, Inc.

International Classification:

A61K031/404
C 07D 4 3/02
C 07D 4 3/14

US Classification:

514/414000, 548/465000

Abstract:

The present invention relates to 4-arylindolinones, as well as pharmaceutical compositions thereof, capable of modulating protein kinase signal transduction in order to regulate, modulate and/or inhibit abnormal cell proliferation. The present invention also relates to methods for treating protein kinase related disorders.

US Patent:

20230130259, Apr 27, 2023

Filed:

Oct 20, 2022

Appl. No.:

18/048378

Inventors:

- San Jose CA, US
Hong Shen - Palo Alto CA, US
Patrick Variot - Los Gatos CA, US
Rajesh Katkar - Milpitas CA, US

International Classification:

H01Q 9/04
H01Q 1/52
H01Q 1/48
H01L 23/552
H01L 23/00
H01L 23/498
H01L 23/31

Abstract:

An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through one or more of the conductive routing traces of the redistribution layer. When the antenna structure is separated from the system board, the integrated device die can be positioned between the antenna structure and the system board, and the integrated device die can be electrically coupled to the antenna structure at least partially through one or more of conductive routing traces of the system board and conductive wire of an interconnect structure between the system board and the antenna structure.

US Patent:

20200243369, Jul 30, 2020

Filed:

Apr 10, 2020

Appl. No.:

16/845455

Inventors:

- Woburn MA, US
Hong Shen - Palo Alto CA, US
Viswanathan Ramanathan - Thousand Oaks CA, US

International Classification:

H01L 21/683
H01L 21/768
H01L 23/58
H01L 23/522
H03H 9/10
H01L 23/13
H03H 3/007
H03H 3/02
H03H 3/08

Abstract:

According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.

US Patent:

20200083202, Mar 12, 2020

Filed:

Nov 14, 2019

Appl. No.:

16/683592

Inventors:

- Woburn MA, US
Hong Shen - Palo Alto CA, US
Viswanathan Ramanathan - Thousand Oaks CA, US

International Classification:

H01L 25/16
H01L 23/06
H03H 3/02
H03H 9/10
H03H 9/05
H03H 9/64
H01L 21/683
H01L 23/48
H01L 23/00
H03H 3/08
H01L 21/306
H01L 23/31
H01L 23/58
H01L 41/047

Abstract:

A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.

US Patent:

20190333815, Oct 31, 2019

Filed:

May 15, 2019

Appl. No.:

16/412893

Inventors:

- Woburn MA, US
Hong Shen - Palo Alto CA, US

International Classification:

H01L 21/768
H01L 23/495
H01L 23/00
H01L 21/683
H01L 23/482

Abstract:

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

US Patent:

20190333816, Oct 31, 2019

Filed:

May 15, 2019

Appl. No.:

16/412929

Inventors:

- Woburn MA, US
Hong Shen - Palo Alto CA, US

International Classification:

H01L 21/768
H01L 23/495
H01L 23/00
H01L 21/683
H01L 23/482

Abstract:

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

US Patent:

20190172903, Jun 6, 2019

Filed:

Feb 11, 2019

Appl. No.:

16/272736

Inventors:

- San Jose CA, US
Hong Shen - Palo Alto CA, US
Rajesh Katkar - Milpitas CA, US

Assignee:

Invensas Corporation - San Jose CA

International Classification:

H01L 49/02
H01L 23/00
H01L 21/56
H01L 23/522
H01L 25/00
H01L 25/16
H01L 25/11
H01L 25/10
H01L 23/498

Abstract:

Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.