Howard M Maassen

US Patent:

6794861, Sep 21, 2004

Filed:

Mar 25, 2002

Appl. No.:

10/106280

Inventors:

Howard M. Maassen - San Jose CA
William A. Fritzsche - Morgan Hill CA

Assignee:

NPTest, LLC - San Jose CA

International Classification:

G01R 2702

US Classification:

3241581

Abstract:

Method and apparatus for calibrating timing accuracy during testing of integrated circuits. An ATE type (automatic test equipment) integrated circuit tester calibrates itself to reference blocks (dummy ICs) that have the same relevant dimensions as the integrated circuits to be tested and have fit into the test fixture. The number of reference blocks required is equal to the number of signal terminals on the integrated circuit to be tested subject to timing calibration where typically the number of signal terminals is less than the total number of signal terminals on the IC being tested and is typically a relatively small number, e. g. , 9. This is useful in the case of high pin count integrated circuits where the pins are grouped into relatively small numbers of pins which are source synchronous. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block in the set. The reference blocks are then cycled through the tester apparatus as if they were an IC under test, resulting in timing calibration.

US Patent:

7212941, May 1, 2007

Filed:

Aug 24, 2004

Appl. No.:

10/924675

Inventors:

Angarai T. Sivaram - Saratoga CA, US
Burnell G. West - Half Moon Bay CA, US
Howard Maassen - San Jose CA, US

Assignee:

Credence Systems Corporation - Milpitas CA

International Classification:

G01R 31/00

US Classification:

702120, 714 37, 714735

Abstract:

A test apparatus implements a method for testing electronic devices that exhibit non-deterministic behavior. The test apparatus includes a high-speed buffer queue for storing data packets. The data packets arrive at one end of the queue and, as they exit at the other end, are compared against expect data packets stored in memory. If the data packet exiting the buffer queue corresponds to response signals generated by the device under test during a non-deterministic (e. g. , idle) state, the expect data packet is not retrieved from memory and the comparison is not made.

US Patent:

7372302, May 13, 2008

Filed:

Jun 28, 2006

Appl. No.:

11/477971

Inventors:

Atsushi Ohshima - Tokyo, JP
Toshihiro Nomura - Yokohama, JP
Howard Maassen - San Jose CA, US

Assignee:

Credence Systems Corporation - Milpitas CA

International Classification:

H03K 19/0175

US Classification:

326 82, 326 16

Abstract:

A driver block for a differential pin driver that supports out-of-band signaling. The driver block includes a main enable switch that is controlled by a high speed driver inhibit (DINH) signal. The main enable switch controls coupling between a main current source and a differential pin driver output stage. The main enable switch is coupled in series with an output select switch that selects between a positive output and a negative output. The driver block also includes a positive enable switch for controlling coupling between the positive output and a positive level shifter that shifts voltages of the positive output. The driver block also includes a negative enable switch for controlling coupling between the negative output and a negative level shifter that shifts voltages of the negative output.

US Patent:

7810005, Oct 5, 2010

Filed:

Oct 31, 2007

Appl. No.:

11/982075

Inventors:

Jean-Yann Gazounaud - St Rambert, FR
Howard Maassen - San Jose CA, US

Assignee:

Credence Systems Corporation - Milpitas CA

International Classification:

G06F 11/00

US Classification:

714744, 714 25, 714742, 714724, 714 32, 714731, 714726, 3241581, 324 731, 700 11, 702117, 702123, 702124, 702125

Abstract:

A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e. g. , processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

US Patent:

8156396, Apr 10, 2012

Filed:

Oct 5, 2010

Appl. No.:

12/898621

Inventors:

Jean-Yann Gazounaud - St Just St Rambert, FR
Howard Maassen - San Jose CA, US

International Classification:

G01R 31/28

US Classification:

714744, 714 25, 714742, 714724, 714 32, 714731, 714726, 714709, 714700, 3241581, 324 731, 700 11, 702117, 702123, 702124, 702125

Abstract:

A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e. g. , processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

US Patent:

20030156545, Aug 21, 2003

Filed:

Feb 18, 2003

Appl. No.:

10/371353

Inventors:

Masashi Shimanouchi - Sunnyvale CA, US
Howard Maassen - San Jose CA, US

International Classification:

H04J001/16

US Classification:

370/241000

Abstract:

Method and apparatus for circuit testing with signal paths providing multiple test configurations. Circuitry for use in testing electronic circuits includes switching circuitry operable to be controlled to make one of a first signal path and a second signal path. The first signal path is configured to carry a signal between a first node and a second node. The second signal path is configured to carry a signal between the first node and a third node. Each of the signal paths includes a portion that is located in pin electronics. The first node is connectable to a first pin of a device under test. The second node is connectable to a second pin of a device under test. The third node is connectable to an electronic instrument.

US Patent:

20060047463, Mar 2, 2006

Filed:

Sep 23, 2004

Appl. No.:

10/948709

Inventors:

A. T. Sivaram - Saratoga CA, US
Howard Maassen - San Jose CA, US

International Classification:

G06F 19/00

US Classification:

702120000, 702117000

Abstract:

An apparatus for testing electronic devices that output high-speed serial data bit streams employs a programmable device to adjust the timing of the strobe so that the data bit stream being analyzed is strobed at or near the center of the bit. The programmable device sets a number of different reference strobe points that are used to strobe the data bit streams. The different reference strobe points span a single bit interval at regular intervals. The programmable device evaluates the strobe readings generated with the different reference strobe points and selects one of them as the one to be used during testing. The selection is made during the initialization phase of testing or intermittently while the test is being carried out.

US Patent:

6492797, Dec 10, 2002

Filed:

Feb 28, 2000

Appl. No.:

09/514708

Inventors:

Howard M. Maassen - San Jose CA
William A. Fritzsche - Morgan Hill CA
Thomas P. Ho - Los Altos CA
Joseph C. Helland - San Jose CA

Assignee:

Schlumberger Technologies, Inc. - San Jose CA

International Classification:

G01R 1132

US Classification:

324 74

Abstract:

A method and apparatus for calibrating tester timing accuracy during testing of integrated circuits. An ATE tester measures itself through reference blocks that have the same relevant dimensions as the integrated circuits to be tested. The number of reference blocks required is equal to the number of signal terminals on an integrated circuit to be tested being subject to timing calibration. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block. Each signal trace used should be closely matched both physically and electrically to the other signal traces used in the set of reference blocks, so that the electrical path length associated with each trace is nearly identical. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel. The fixture provides electrical connection of the reference block to the loadboard, and ultimately, the tester.