Howard N Tran

US Patent:

6438181, Aug 20, 2002

Filed:

May 28, 1999

Appl. No.:

09/321682

Inventors:

Jyoti Setlur - Irvine CA
Howard Tran - Downey CA

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H04L 2706

US Classification:

375341, 375262, 714795, 704242, 370342

Abstract:

An apparatus and method thereof for storing and retrieving information in a Viterbi decoder. The apparatus includes a bus and a branch metric generator unit coupled to the bus. The branch metric generator unit generates metrics by measuring a difference between an encoded data bit and an expected data bit calculated using a convolutional code. A memory unit is also coupled to the bus. The memory unit includes a first register and a second register for storing the metrics. A parity bit is used to indicate a register for storing the metrics. In a first stage of the Viterbi decoder, a metric for a first state is stored at a first address in the first register and a metric for a second state is stored at a second address in the second register. The first state and the second state each branch to a third state and a fourth state in a trellis code of the Viterbi decoder.

US Patent:

6542492, Apr 1, 2003

Filed:

May 28, 1999

Appl. No.:

09/322293

Inventors:

Howard Tran - Downey CA
Jyoti Setlur - Irvine CA

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G21C 2300

US Classification:

370342, 370335, 370329, 370350, 370341, 455452, 455458, 714795

Abstract:

A method and system of initializing state metrics for traffic, paging, and sync channels to enhance Viterbi decoder performance. Specifically, one embodiment of the present invention includes a common circuit adapted for initializing state metric data of a traffic channel, a paging channel, and a sync channel within a Code Division Multiple Access (CDMA) system without compromising performance of any channel. The common circuit comprises a multiplexer stage coupled to receive a first signal and a second signal. Furthermore, the common circuit comprises a logic stage coupled to receive a plurality of signals. Additionally, the logic stage is also coupled to the multiplexer stage. As such, the multiplexer stage and the logic stage are adapted to initialize state metric data of any one of a traffic channel, a paging channel, and a sync channel within a Code Division Multiple Access (CDMA) system. It is appreciated that the common circuit does not compromise performance of any one of the traffic channel, the paging channel, and the sync channel.

US Patent:

6587519, Jul 1, 2003

Filed:

May 28, 1999

Appl. No.:

09/322703

Inventors:

Howard Tran - Downey CA
Jyoti Setlur - Irvine CA

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H03D 100

US Classification:

375341

Abstract:

An apparatus and method thereof for decoding a stream of binary digits encoded according to a convolutional code. The apparatus includes a bus, a N-bit counter coupled to the bus, and a trellis code generator coupled to the bit counter. The bit counter is adapted to generate a sequence of N binary bits. The trellis code generator includes a first logical gate and a second logical gate. The trellis code generator is adapted to specify a first set of binary digits from the sequence of N binary bits and to pass the first set of binary digits through the first logical gate to produce a first binary value. The trellis code generator is also adapted to specify a second set of binary digits from the sequence of N bits and to pass the second set of binary digits through the second logical gate to produce a second binary value. The first set of binary digits are particularly specified so that the first binary value emulates a first value of a first encoded bit that would have been determined using the convolutional code. Similarly, the second set of binary digits is specified so that the second binary value emulates a first value of a second encoded bit that would have been determined using the convolutional code.

US Patent:

20010048635, Dec 6, 2001

Filed:

Jul 12, 2001

Appl. No.:

09/905219

Inventors:

Tien Nguyen - San Digeo CA, US
John McDonough - La Jolla CA, US
David (DACHING) Chen - Irvine CA, US
Howard (HAU) Tran - Downey CA, US

International Classification:

G11C008/00
G11C007/00

US Classification:

365/233000, 365/221000

Abstract:

An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S). When in a secondary power savings mode, the pulse swallower produces an output signal having a frequency of chiprate which is used to maintain CDMA network time, permitting the analog transceiver to be powered down during the secondary mode. In another embodiment of the invention, the external clock signal from the analog transceiver having a frequency of chiprate(S) is multiplied by (n) to produce the primary digital transceiver clock signal.

US Patent:

62890670, Sep 11, 2001

Filed:

May 28, 1999

Appl. No.:

9/322282

Inventors:

Tien Q. Nguyen - San Diego CA
John G. McDonough - La Jolla CA
David Chen - Irvine CA
Howard Thien Tran - Downey CA

Assignee:

Dot Wireless, Inc. - San Diego CA
VLSI Technology, Inc. - San Jose CA

International Classification:

H04L 2536
H04L 2540
H04L 700

US Classification:

375372

Abstract:

An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S).