Hung Miao Li

US Patent:

6693985, Feb 17, 2004

Filed:

Oct 26, 2001

Appl. No.:

10/043886

Inventors:

Hung Sung Li - Sunnyvale CA
Ook Kim - Palo Alto CA

Assignee:

Silicon Image - Sunnyvale CA

International Classification:

H04L 700

US Classification:

375355, 375371, 327144

Abstract:

Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.

US Patent:

6717478, Apr 6, 2004

Filed:

Nov 20, 2001

Appl. No.:

09/989587

Inventors:

Ook Kim - Palo Alto CA
Hung Sung Li - Sunnyvale CA
Inyeol Lee - Cupertino CA
Gyudong Kim - San Jose CA
Yongman Lee - Pleasanton CA

Assignee:

Silicon Image - Sunnyvale CA

International Classification:

H03B 2700

US Classification:

331 57, 331 46

Abstract:

A voltage controlled oscillator (âVCOâ) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.

US Patent:

6809567, Oct 26, 2004

Filed:

Nov 20, 2001

Appl. No.:

09/989645

Inventors:

Ook Kim - Palo Alto CA
Hung Sung Li - Sunnyvale CA
Inyeol Lee - Cupertino CA
Gyudong Kim - San Jose CA
Yongman Lee - Pleasanton CA

Assignee:

Silicon Image - Sunnyvale CA

International Classification:

H03L 700

US Classification:

327160, 327115, 327117, 327295

Abstract:

A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (âVCOâ) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e. g. , a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.