Ian Patrick Shaeffer from Los Gatos, CA, age 50

Resumes

Principal Architect, Macintosh Computers

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Location:

San Francisco, CA

Industry:

Computer Hardware

Work:

Samsung Semiconductor - San Jose, CA since Sep 2012
Director, System Architecture Lab
Rambus Inc. Jan 2005 - Sep 2012
Senior Principal Engineer - Architecture
Sun Microsystems Aug 2002 - Jan 2005
Engineering Manager
Afara Websystems Jan 2002 - Aug 2002
Lead Design Engineer
inSilicon Nov 2000 - Dec 2001
Systems Lead Engineer

Education:

Stanford University 1997 - 2000
Masters, Master of Science In Electrical Engineering, Architecture University of Southern California 1991 - 1996
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering, Recording Arts

Skills:

Hardware Architecture
Signal Integrity
Semiconductors
System Architecture
Asic
Dram
Ddr3
Debugging
Soc
Computer Architecture
Processors
Microprocessors
Ddr2
Patents
Verilog
Ic
Flash Memory
Circuit Design
Computer Hardware
Simulations
Testing
Fpga
Memory
Technical Leadership
Mixed Signal
Analog
Eda
Usb
Serdes
Cmos
Hardware
Silicon
Application Specific Integrated Circuits
Low Power Design
Analog Circuit Design
Architecture

Languages:

English
Spanish

Ian Shaeffer

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Us Patents

Connection Block For Interfacing A Plurality Of Printed Circuit Boards
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US Patent:

6460170, Oct 1, 2002
Filed:

Apr 29, 2000
Appl. No.:

09/561808
Inventors:

Ian P. Shaeffer - San Jose CA
Everett Basham - Sunnyvale CA
Assignee:

Hewlett Packard Company - Palo Alto CA
International Classification:

G06F 1750
US Classification:

716 15, 257 2, 257 8, 257 9, 438 7, 438 8, 438 9, 438 10, 361704, 361707, 361719, 361720
Abstract:

A system and method is described for providing a robust mechanical and electrical connection between two or more circuit boards which may be employed for diagnostic purposes and/or for permanent connections. A spacer block, connection block, or pedestal, preferably made of PCB type material is preferably disposed between two PCBs. The pedestal is preferably dimensioned to space the two PCBs far enough apart that the surface mount components on two boards connected employing the inventive pedestal do not interfere with one another. The pedestal preferably provides for ample signal density and signal quality because of the block thickness and availability of insulation within the pedestal.

System And Method For Single Point Observability Of A Dual-Mode Control Interface
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US Patent:

6587965, Jul 1, 2003
Filed:

Apr 29, 2000
Appl. No.:

09/563004
Inventors:

Ian P. Shaeffer - San Jose CA
Jeffrey C. Swanson - Sunnyvale CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 1100
US Classification:

714 28, 703 28
Abstract:

The present invention provides for a method and system for external observation of a dual mode control interface, via a single point of entry/exit from a chip. In operation, data is sent into and retrieved from a chip using a single point on the chip. Multiple test methods can be used with the proper test method selected by an established hierarchy of methods. In one embodiment, an impedance is shown for control purposes between test methods.

Printed Circuit Board Having Solder Bridges For Electronically Connecting Conducting Pads And Method Of Fabricating Solder Bridges
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US Patent:

6664482, Dec 16, 2003
Filed:

May 1, 2000
Appl. No.:

09/561591
Inventors:

Ian P. Shaeffer - San Jose CA
Everett Basham - Sunnyvale CA
Christopher D. Price - Campbell CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

H05K 111
US Classification:

174261, 174256
Abstract:

A method of fabricating a zero signal degradation solder bridge electrical connection for connecting adjacent conducting pads of a printed circuit board, and a printed circuit board having at least one of these solder bridge electrical connections. In the method, a stencil, having an opening that corresponds to the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the adjacent conducting pads, is placed on the surface of printed circuit board. Solder paste is then applied to the stencil such that the solder paste flows through the stencil opening and onto the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the pads. The stencil is then removed and the printed circuit board is subjected to reflow soldering, thereby fabricating a printed circuit board having a solder bridge electrical connector between adjacent conducting pads.

Method Of Fabricating A Substantially Zero Signal Degradation Electrical Connection On A Printed Circuit Broad
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US Patent:

7140531, Nov 28, 2006
Filed:

Sep 3, 2003
Appl. No.:

10/654177
Inventors:

Ian P. Shaeffer - San Jose CA, US
Everett Basham - Sunnyvale CA, US
Christopher D. Price - Campbell CA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

B23K 31/02
US Classification:

2282481, 29830
Abstract:

A method of fabricating a substantially zero signal degradation electrical connection on a printed circuit board includes providing a printed circuit board defined by a dielectric structure core. The dielectric structure core has a first surface, which includes a first connecting pad having an edge and a second connecting pad having an edge separated from an adjacent to the edge of the first conducting pad. The edges of the first and second conducting pads define therebetween a surface area of the first surface. A solder paste is applied on the first and second conducting pads and on the first surface of the dielectric structure core. The solder paste at least partially covers the surface area of the first surface between the edges of the first and second conducting pads, thereby forming a substantially zero signal degradation electrical connection between the first and second conducting pads.

Method And Apparatus For Data Capture On A Bi-Directional Bus
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US Patent:

7196948, Mar 27, 2007
Filed:

Mar 7, 2005
Appl. No.:

11/074462
Inventors:

Sunil K. Vemula - Sunnyvale CA, US
Francis X. Schumacher - Palo Alto CA, US
Ian P. Shaeffer - San Jose CA, US
Assignee:

Sun Microsystems, Inc . - Santa Clara CA
International Classification:

G11C 7/00
US Classification:

365193, 365191, 365194, 365233
Abstract:

A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with issuing a read command. Then, a strobe signal is transitioned from a mid-rail state. In one embodiment, the strobe signal is transitioned to a logical low state. A read enable signal is then transitioned prior to a first falling edge of the strobe signal. The strobe signal represents an earliest availability for valid read data being available. The valid read data is read in response to the read enable signal transition. A microprocessor and a system wherein data is read over a bi-directional bus are included.

Memory Controller With Staggered Request Signal Output
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US Patent:

7321524, Jan 22, 2008
Filed:

Oct 17, 2005
Appl. No.:

11/252957
Inventors:

Ian P. Shaeffer - San Jose CA, US
Bret Stott - Menlo Park CA, US
Benedict C. Lau - San Jose CA, US
Assignee:

Rambus Inc. - Los Altos CA
International Classification:

G11C 8/00
US Classification:

365233, 365191, 365194, 365201, 36523008
Abstract:

A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Stencil Device For Accurately Applying Solder Paste To A Printed Circuit Board
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US Patent:

7412923, Aug 19, 2008
Filed:

Sep 3, 2003
Appl. No.:

10/654066
Inventors:

Ian P. Shaeffer - San Jose CA, US
Everett Basham - Sunnyvale CA, US
Christopher D. Price - Campbell CA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

B05C 17/06
US Classification:

101127, 118213, 118406, 427282
Abstract:

A stencil device ensures that solder paste is accurately applied to a printed circuit board to create a substantially zero signal degradation solder bridge electrical connection. The printed circuit board is defined by a dielectric structure core having a first surface which further includes a first conducting pad having an edge and a second conducting edge having an edge separated from and adjacent to the edge of the first conducting pad. The edges of the first and second conducting pads define therebetween a surface area of the first surface. The stencil device includes a stencil plate member defining a first opening sized to substantially correspond to the first conducting pad, a second opening sized to substantially correspond to the second conducting pad, and a third opening. The third opening links the first opening to the second opening at a size to correspond to a partial portion of the surface area of the first surface between the edges of the first and second conducting pads. The stencil device ensures that solder paste flows through the first, second, and third openings onto the first and second conducting pads and the first surface of the dielectric structure core to form a substantially zero signal degradation electrical connection between the first and second conducting pads.

Integrated Circuit With Graduated On-Die Termination
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US Patent:

7486104, Feb 3, 2009
Filed:

Jun 2, 2006
Appl. No.:

11/422022
Inventors:

Kyung Suk Oh - Campbell CA, US
Ian P. Shaeffer - San Jose CA, US
Assignee:

RAMBUS Inc. - Los Altos CA
International Classification:

H03K 17/16
US Classification:

326 30, 326 83, 326 26
Abstract:

An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.