Ioannis T Schoinas

US Patent:

6662276, Dec 9, 2003

Filed:

Dec 29, 2000

Appl. No.:

09/751579

Inventors:

Ioannis T. Schoinas - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711145, 711144, 711156

Abstract:

An embodiment of the present invention includes a cache and a controller in a non uniform memory architecture (NUMA) system. The cache stores a plurality of entries, each of which contains an entry type indicating if the entry is one of a normal entry and a directory entry. The controller processes an access request from a processor for a memory block using the plurality of entries.

US Patent:

6971098, Nov 29, 2005

Filed:

Jun 27, 2001

Appl. No.:

09/891522

Inventors:

Manoj Khare - Saratoga CA, US
Akhilesh Kumar - Santa Clara CA, US
Ioannis Schoinas - Portland OR, US
Lily Pao Looi - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F009/46

US Classification:

718101, 718100, 718102, 718105

Abstract:

Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received. If the request complete message for the previously received ordered group request has not been received and the next received ordered group request in the same ordered group is at least one of a un-ordered request and a forward-ordered request, then the next received ordered group request may be forwarded to the destination agent after the request complete message for the previously received at least one of a forward-ordered request and a sequential-ordered request issued on a different path at the ordering fork has been received.

US Patent:

7127566, Oct 24, 2006

Filed:

Dec 18, 2003

Appl. No.:

10/741721

Inventors:

Siva Ramakrishnan - Beaverton OR, US
Ioannis Schoinas - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/16

US Classification:

711152

Abstract:

In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.

US Patent:

7127567, Oct 24, 2006

Filed:

Dec 18, 2003

Appl. No.:

10/741722

Inventors:

Siva Ramakrishnan - Beaverton OR, US
Ioannis Schoinas - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/16

US Classification:

711152

Abstract:

In some embodiments, a memory transaction is received that was sent over an unordered interconnect. A determination is made as to whether an address conflict exists between the memory transaction and another memory transaction. If the address conflict exists the memory transaction is forwarded only after waiting until the conflict is resolved. Other embodiments are described and claimed.

US Patent:

7222203, May 22, 2007

Filed:

Dec 8, 2003

Appl. No.:

10/731171

Inventors:

Rajesh S. Madukkarumukumana - Portland OR, US
Ioannis Schoinas - Portland OR, US
Gilbert Neiger - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/24
G06F 12/00

US Classification:

710260, 710269, 710 48, 718100, 718 1, 711151

Abstract:

The present disclosure relates to the handling of interrupts in a environment that utilizes virtual machines, and, more specifically, to the steering of interrupts between multiple logical processors running virtual machines.

US Patent:

7257682, Aug 14, 2007

Filed:

Jun 22, 2006

Appl. No.:

11/473589

Inventors:

Siva Ramakrishnan - Beaverton OR, US
Ioannis Schoinas - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/16

US Classification:

711152

Abstract:

In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.

US Patent:

7328368, Feb 5, 2008

Filed:

Mar 12, 2004

Appl. No.:

10/801448

Inventors:

Phanindra K. Mannava - Folsom CA, US
Victor W. Lee - San Jose CA, US
Akhilesh Kumar - Sunnyvale CA, US
Doddaballapur N. Jayasimha - Sunnyvale CA, US
Ioannis T. Schoinas - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 8, 714 17, 714 18, 714 43, 714 56

Abstract:

In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.

US Patent:

7334107, Feb 19, 2008

Filed:

Sep 30, 2004

Appl. No.:

10/956206

Inventors:

Ioannis Schoinas - Portland OR, US
Rajesh Madukkarumukumana - Portland OR, US
Gilbert Neiger - Portland OR, US
Richard Uhlig - Hillsboro OR, US
Balaji Vembu - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/28

US Classification:

711207, 711118, 711154

Abstract:

An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.