Iqbal H Bhatti

US Patent:

6907231, Jun 14, 2005

Filed:

Apr 15, 2002

Appl. No.:

10/122458

Inventors:

Iqbal S. Bhatti - Los Angeles CA, US

Assignee:

Broadcom, Corp. - Irvine CA

International Classification:

H04Q011/12
H04B001/04

US Classification:

4551271, 455121

Abstract:

An on-chip impedance matching includes a transistor, an inductor, and a capacitive divider. The gate of the transistor is operably coupled to receive input signals; the source of the transistor is coupled to a first DC voltage potential; and the drain of the transistor is operably coupled to the inductor. The other end of the inductor is operably coupled to a second DC voltage potential. The capacitive divider includes matched capacitors that, in combination with the inductor, provide for substantially lossless on-chip impedance matching, where a tap of the capacitive divider provides an output of the on-chip impedance matching power amplifier. In addition, the capacitance of the capacitive divider and the inductance of the inductor are tuned to provide a tank circuit for the on-chip impedance matching power amplifier.

US Patent:

7088214, Aug 8, 2006

Filed:

Dec 4, 2003

Appl. No.:

10/727422

Inventors:

Jesus A. Castaneda - Marina Del Ray CA, US
Iqbal S. Bhatti - Los Angeles CA, US
Hung Yu Yang - Los Angeles CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01F 5/00

US Classification:

336200

Abstract:

An on-chip multiple tap transformer balun includes a 1winding and a 2winding having two portions. The 1winding is on a 1layer of an integrated circuit and is operably coupled for a single ended signal. The 1and 2portions of the 2winding are on a 2layer of the integrated circuit. The 1portion of the 2winding includes a 1node, a 2node, and a tap. The 1node is operably coupled to receive a 1leg of a 1differential signal and the 2node is coupled to a reference potential. The tap of the 1portion is operably coupled for a 1leg of a 2differential signal. The 2portion of the 2winding includes a 1node, 2node, and tap. The 1node is operably coupled to receive a 2leg of the 1differential signal and the 2node is operably coupled to the reference potential. The tap of the 2portion is coupled for a 2leg of the 2differential signal. The 1and 2portions of the 2winding are symmetrical with respect to the 1and 2nodes and with respect to the tap nodes.

US Patent:

7129784, Oct 31, 2006

Filed:

Oct 28, 2004

Appl. No.:

10/975240

Inventors:

Iqbal Bhatti - Los Angeles CA, US
Jesus Castaneda - Los Angeles CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F 3/68

US Classification:

330295, 330195

Abstract:

A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

US Patent:

7184735, Feb 27, 2007

Filed:

Aug 21, 2003

Appl. No.:

10/645026

Inventors:

Iqbal S. Bhatti - Los Angeles CA, US
Rozi (Razieh) Roufoogaran - Marina Del Rey CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/18

US Classification:

455292, 455334

Abstract:

A radio frequency circuit includes a first differential RF path and a second differential path. The first differential RF path includes at least one RF block that includes a first differential section and a second differential section, wherein the first differential section is symmetrical with the second differential section. The second differential RF path includes at least one RF block that includes a first differential section and a second differential section, wherein the first differential section is symmetrical with the second differential section. The first and second half differential sections of the at least one RF block of the first differential RF path are symmetrically placed on at least one layer around the first and second half differential sections of the at least one RF block of the second differential RF path, wherein the first and second half differential sections of the at least one RF block of the second differential RF path are fabricated on the at least one layer.

US Patent:

7209727, Apr 24, 2007

Filed:

Jun 12, 2003

Appl. No.:

10/459985

Inventors:

Jesus A. Castaneda - Marina Del Ray CA, US
Iqbal S. Bhatti - Los Angeles CA, US
Razieh Roufoogaran - Marina Del Ray CA, US
Hung Yu Yang - Darien IL, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/16

US Classification:

455341, 455 73, 455 78, 455 83

Abstract:

An integrated RF front-end architecture is disclosed. Such an integrated RF front-end architecture includes a multi-tap balun, a low noise amplifier and a power amplifier core. The multi-tap balun includes a single-ended primary winding and a symmetrical multi-tap secondary winding, wherein the single-ended primary winding is operably coupled to an antenna. The low noise amplifier is coupled to a first set of taps of the symmetrical multi-tap secondary winding. The power amplifier core is coupled to a second set of taps of the symmetrical multi-tap secondary winding and can be a two stage amplifier having a driver stage and an output stage. The multi-tap balun, low noise amplifier and power amplifier core can be on-chip components or can be fabricated to be discrete components on a printed circuit board.

US Patent:

7215932, May 8, 2007

Filed:

May 3, 2005

Appl. No.:

11/120763

Inventors:

Iqbal S. Bhatti - Los Angeles CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04Q 11/12
H04B 1/04

US Classification:

4551271, 455121

Abstract:

An on-chip impedance matching includes a transistor and a tank circuit. The transistor is operably coupled to receive an input signal. The tank circuit is operably coupled to the transistor, wherein a tap of the tank circuit provides an output of the on-chip impedance matching power amplifier, wherein the tank circuit is tuned with respect to an antenna load of the on-chip impedance matching power amplifier.

US Patent:

7365602, Apr 29, 2008

Filed:

Oct 26, 2006

Appl. No.:

11/553190

Inventors:

Iqbal Bhatti - Los Angeles CA, US
Jesus Castaneda - Los Angeles CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F 3/68

US Classification:

330295, 330195, 330 51, 330124 D, 330124 R

Abstract:

A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

US Patent:

7526256, Apr 28, 2009

Filed:

May 25, 2005

Appl. No.:

11/136850

Inventors:

Iqbal Bhatti - Rancho Palos Verdes CA, US
Jesus Castaneda - Los Angeles CA, US
Bojko F. Marholev - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/38
H04B 1/44
H04B 3/00
H04L 25/00
H04L 25/06
H04L 25/10
H01Q 9/28
H03H 5/00

US Classification:

455 73, 455 78, 455 83, 375258, 375318, 343795, 333 25

Abstract:

An apparatus and method for allowing two different signal paths to be coupled to a multi-tap transformer balun. The multi-tap transformer has a first port, which is coupled to a single antenna, and two or more differential secondary ports. Each port has one or more taps, which are optimized separately for each of the signal paths, allowing each of the two or more signal paths to operate in different frequency bands. Use of the method of the invention can decrease the number of external components and integrated circuit package pins, and reduce the area required for each signal path on an integrated circuit die, a printed circuit board, or the like.