Jack Kang Lun Cheung

US Patent:

6456126, Sep 24, 2002

Filed:

May 25, 2001

Appl. No.:

09/865871

Inventors:

Jack Siu Cheung Lo - San Jose CA
Shankar Lakkapragada - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03B 1900

US Classification:

327116, 327122

Abstract:

An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

US Patent:

6744289, Jun 1, 2004

Filed:

Jul 10, 2002

Appl. No.:

10/193070

Inventors:

Andy T. Nguyen - San Jose CA
Jack Siu Cheung Lo - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 104

US Classification:

327115, 327117

Abstract:

A clock divider circuit that adds little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are provided to a multiplexer circuit. Under the direction of the control circuit, the multiplexer circuit passes selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the clock divider circuit. When neither the true nor the complement clock signal is passed by the multiplexer, a keeper circuit retains the value already present at the output clock terminal.

US Patent:

6864727, Mar 8, 2005

Filed:

Jan 10, 2003

Appl. No.:

10/340494

Inventors:

Jack Siu Cheung Lo - San Jose CA, US
Shankar Lakkapragada - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03B019/00

US Classification:

327116, 327119

Abstract:

An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

US Patent:

6362669, Mar 26, 2002

Filed:

Apr 10, 2000

Appl. No.:

09/546897

Inventors:

Jack Siu Cheung Lo - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03L 700

US Classification:

327143, 327198

Abstract:

A power-on reset (POR) circuit that delays de-assertion a POR control signal in an IC device such that, when unstable power levels are detected, the POR control signal is maintained in an asserted condition until the IC device is fully reset. During a start-up phase of the IC device operation, the POR control circuit maintains the POR control signal in the asserted condition for a delay period whose length is determined, in part, by the amount of noise in the applied power. After the internal voltage of the IC device achieves a steady state for a suitable period of time, the POR control circuit de-asserts the POR control signal, thereby initiating configuration of the IC device. Subsequently, if a low power condition is detected, the POR control circuit asserts the POR control signal, and maintains the POR control signal in the asserted condition for a pre-defined delay period after the low-power event is detected, thereby allowing the IC device to fully reset.