Jack Y Chu

US Patent:

6350993, Feb 26, 2002

Filed:

Mar 12, 1999

Appl. No.:

09/267323

Inventors:

Jack Oon Chu - Manhasset Hills NY
Richard Hammond - Dobbs Ferry NY
Khalid EzzEldin Ismail - Yorktown Heights NY
Steven John Koester - Ossining NY
Patricia May Mooney - Mt. Kisco NY
John A. Ott - Greenwood Lake NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2906

US Classification:

257 19, 257 18, 257 20, 257190, 257191, 257192

Abstract:

A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

US Patent:

6425951, Jul 30, 2002

Filed:

Aug 6, 1999

Appl. No.:

09/369995

Inventors:

Jack Oon Chu - Astoria NY
Khalid Ezzeldin Ismail - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C30B 3306

US Classification:

117 3, 117 88, 117 89, 117 93

Abstract:

An apparatus for forming a portion of an electronic device is described incorporating an Ultra High Vacuum-Chemical Vapor Deposition (UHV-CVD) system, a Low Pressure-Chemical Vapor Deposition (LP-CVD) system, and an Ultra High Vacuum (UHV) transfer system. A method for passivating a semiconductor substrate is described incorporating growing silicon containing layers, flowing a hydrogen containing gas and lowering the substrate temperature below 400Â C. A method for removing native oxide is described. A method for growing a continuous epitaxial layer while performing a deposition interrupt is described. A method for forming a Si/Si oxide interface is described having low interface trap density. A method for forming a Si/Si oxide/p++ polysilicon gate stack. The invention overcomes the problem of requiring silicon containing wafers being dipped in HF acid prior to CVD processing.

US Patent:

6426265, Jul 30, 2002

Filed:

Jan 30, 2001

Appl. No.:

09/774126

Inventors:

Jack Oon Chu - Manhasset Hills NY
Douglas Duane Coolbaugh - Essex Junction VT
James Stuart Dunn - Jericho VT
David R. Greenberg - White Plains NY
David L. Harame - Essex Junction VT
Basanth Jagannathan - Stormville NY
Robb Allen Johnson - South Burlington VT
Louis D. Lanzerotti - Burlington VT
Kathryn Turner Schonenberg - New Fairfield CT
Ryan Wayne Wuthrich - Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21331

US Classification:

438312, 438357

Abstract:

A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

US Patent:

6649492, Nov 18, 2003

Filed:

Feb 11, 2002

Appl. No.:

10/073562

Inventors:

Jack O. Chu - Manhasset NY
Khaled Ismail - Giza, EG

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2120

US Classification:

438478, 438479, 438483, 438459

Abstract:

A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

US Patent:

6723621, Apr 20, 2004

Filed:

Jun 30, 1997

Appl. No.:

08/885611

Inventors:

Frank Cardone - Yonkers NY
Jack Oon Chu - Astoria NY
Khalid EzzEldin Ismail - White Plains NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2120

US Classification:

438478, 438503

Abstract:

A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5Ã10 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 from the first layer of greater than 1Ã10 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0. 5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFETs, and HBTs.

US Patent:

6743651, Jun 1, 2004

Filed:

Apr 23, 2002

Appl. No.:

10/128794

Inventors:

Jack O. Chu - Manhasset Hills NY
Feng-Yi Huang - Hacienda Heights CA
Steven J. Koester - Ossining NY
Devendra K. Sadana - Pleasantville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438 46, 438 47, 438149, 438235, 438311, 438312, 438966, 438967

Abstract:

A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate is provided by implanting oxygen into a Si/SiGe multilayer heterostructure which comprises alternating Si and SiGe layers. Specifically, the high quality, relaxed SiGe-on-insulator is formed by implanting oxygen ions into a multilayer heterostructure which includes alternating layers of Si and SiGe. Following, the implanting step, the multilayer heterostructure containing implanted oxygen ions is annealed, i. e. , heated, so as to form a buried oxide region predominately within one of the Si layers of the multilayer structure.

US Patent:

6750119, Jun 15, 2004

Filed:

Apr 20, 2001

Appl. No.:

09/838892

Inventors:

Jack Oon Chu - Manhasset Hills NY
Basanth Jagannathan - Stormville NY
Alfred Grill - White Plains NY
Bernard Steele Meyerson - Yorktown Heights NY
John Albrecht Ott - Greenwood Lake NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2120

US Classification:

438479, 438483, 42725528, 4272491

Abstract:

A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350Â C. to 750Â C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon 10 cm , the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850Â C. and rapid thermal anneal temperatures to 1000Â C.

US Patent:

6774010, Aug 10, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/769170

Inventors:

Jack Oon Chu - Manhasset Hills NY
Alfred Grill - White Plains NY
Katherine L. Saenger - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2972

US Classification:

438458, 438455, 438459, 257317, 257318, 257319, 257347, 257360

Abstract:

A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a âtransferableâ device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer described above.